blob: 54b7028c56043606540bee4e46d30024e4415183 [file] [log] [blame]
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +00001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2010 DAVE Srl <www.dave.eu>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +00006 */
7
8/*
9 * ifm AC14xx (MPC5121e based) board configuration file
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_AC14XX 1
Anatolij Gustschin37cf49c2014-10-21 13:47:02 +020016#define CONFIG_DISPLAY_BOARDINFO
17#define CONFIG_SYS_GENERIC_BOARD
18
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000019/*
20 * Memory map for the ifm AC14xx board:
21 *
22 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
23 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
24 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
25 * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx)
26 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
27 */
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_E300 1 /* E300 Family */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000033
34#define CONFIG_SYS_TEXT_BASE 0xFFF00000
35
36#if defined(CONFIG_VIDEO)
37#define CONFIG_CFB_CONSOLE
38#define CONFIG_VGA_AS_SINGLE_DEVICE
39#endif
40
41#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */
42#define SCFR1_IPS_DIV 2
43#define SCFR1_LPC_DIV 2
44#define SCFR1_NFC_DIV 2
45#define SCFR1_DIU_DIV 240
46
47#define CONFIG_MISC_INIT_R
48
49#define CONFIG_SYS_IMMR 0x80000000
50#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
51
52/* more aggressive 'mtest' over a wider address range */
53#define CONFIG_SYS_ALT_MEMTEST
54#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */
55#define CONFIG_SYS_MEMTEST_END 0x0FE00000
56
57/*
58 * DDR Setup - manually set all parameters as there's no SPD etc.
59 */
60#define CONFIG_SYS_DDR_SIZE 256 /* MB */
61#define CONFIG_SYS_DDR_BASE 0x00000000
62#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
63#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
64
65/*
Gerhard Sittigb5992e72013-06-05 14:51:06 +020066 * DDR Controller Configuration
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +000067 *
68 * SYS_CFG:
69 * [31:31] MDDRC Soft Reset: Diabled
70 * [30:30] DRAM CKE pin: Enabled
71 * [29:29] DRAM CLK: Enabled
72 * [28:28] Command Mode: Enabled (For initialization only)
73 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
74 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
75 * [20:19] Read Test: DON'T USE
76 * [18:18] Self Refresh: Enabled
77 * [17:17] 16bit Mode: Disabled
78 * [16:13] Ready Delay: 2
79 * [12:12] Half DQS Delay: Disabled
80 * [11:11] Quarter DQS Delay: Disabled
81 * [10:08] Write Delay: 2
82 * [07:07] Early ODT: Disabled
83 * [06:06] On DIE Termination: Disabled
84 * [05:05] FIFO Overflow Clear: DON'T USE here
85 * [04:04] FIFO Underflow Clear: DON'T USE here
86 * [03:03] FIFO Overflow Pending: DON'T USE here
87 * [02:02] FIFO Underlfow Pending: DON'T USE here
88 * [01:01] FIFO Overlfow Enabled: Enabled
89 * [00:00] FIFO Underflow Enabled: Enabled
90 * TIME_CFG0
91 * [31:16] DRAM Refresh Time: 0 CSB clocks
92 * [15:8] DRAM Command Time: 0 CSB clocks
93 * [07:00] DRAM Precharge Time: 0 CSB clocks
94 * TIME_CFG1
95 * [31:26] DRAM tRFC:
96 * [25:21] DRAM tWR1:
97 * [20:17] DRAM tWRT1:
98 * [16:11] DRAM tDRR:
99 * [10:05] DRAM tRC:
100 * [04:00] DRAM tRAS:
101 * TIME_CFG2
102 * [31:28] DRAM tRCD:
103 * [27:23] DRAM tFAW:
104 * [22:19] DRAM tRTW1:
105 * [18:15] DRAM tCCD:
106 * [14:10] DRAM tRTP:
107 * [09:05] DRAM tRP:
108 * [04:00] DRAM tRPA
109 */
110
111/*
112 * NOTE: although this board uses DDR1 only, the common source brings defaults
113 * for DDR2 init sequences, that's why we have to keep those here as well
114 */
115
116/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
117#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0))
118
119#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
120 | (1 << 31) /* RST_B */ \
121 | (1 << 30) /* CKE */ \
122 | (1 << 29) /* CLK_ON */ \
123 | (0 << 28) /* CMD_MODE */ \
124 | (5 << 25) /* DRAM_ROW_SELECT */ \
125 | (5 << 21) /* DRAM_BANK_SELECT */ \
126 | (0 << 18) /* SELF_REF_EN */ \
127 | (0 << 17) /* 16BIT_MODE */ \
128 | (4 << 13) /* RDLY */ \
129 | (1 << 12) /* HALF_DQS_DLY */ \
130 | (0 << 11) /* QUART_DQS_DLY */ \
131 | (1 << 8) /* WDLY */ \
132 | (0 << 7) /* EARLY_ODT */ \
133 | (0 << 6) /* ON_DIE_TERMINATE */ \
134 | (0 << 5) /* FIFO_OV_CLEAR */ \
135 | (0 << 4) /* FIFO_UV_CLEAR */ \
136 | (0 << 1) /* FIFO_OV_EN */ \
137 | (0 << 0) /* FIFO_UV_EN */ \
138 )
139
140#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124
141#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147
142#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864
143
144/* register address only, i.e. template without values */
145#define CONFIG_SYS_MICRON_BMODE 0x01000000
146#define CONFIG_SYS_MICRON_EMODE 0x01010000
147#define CONFIG_SYS_MICRON_EMODE2 0x01020000
148#define CONFIG_SYS_MICRON_EMODE3 0x01030000
149/*
150 * values for mode registers (without mode register address)
151 */
152/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
153#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062
154#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100
155/* DLL enable, reduced drive strength */
156#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002
157
158#define CONFIG_SYS_DDRCMD_NOP 0x01380000
159#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
160#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \
161 (0 << 22) | /* DRAM_CS */ \
162 (0 << 21) | /* DRAM_RAS */ \
163 (0 << 20) | /* DRAM_CAS */ \
164 (0 << 19) | /* DRAM_WEB */ \
165 (1 << 16) | /* DRAM_BS[2:0] */ \
166 (0 << 15) | /* */ \
167 (0 << 12) | /* A12->out */ \
168 (0 << 11) | /* A11->RDQS */ \
169 (0 << 10) | /* A10->DQS# */ \
170 (0 << 7) | /* OCD program */ \
171 (0 << 6) | /* Rtt1 */ \
172 (0 << 3) | /* posted CAS# */ \
173 (0 << 2) | /* Rtt0 */ \
174 (1 << 1) | /* ODS */ \
175 (0 << 0) /* DLL */ \
176 )
177#define CONFIG_SYS_MICRON_EMR2 0x01020000
178#define CONFIG_SYS_MICRON_EMR3 0x01030000
179#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
180#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
181#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \
182 (0 << 22) | /* DRAM_CS */ \
183 (0 << 21) | /* DRAM_RAS */ \
184 (0 << 20) | /* DRAM_CAS */ \
185 (0 << 19) | /* DRAM_WEB */ \
186 (1 << 16) | /* DRAM_BS[2:0] */ \
187 (0 << 15) | /* */ \
188 (0 << 12) | /* A12->out */ \
189 (0 << 11) | /* A11->RDQS */ \
190 (1 << 10) | /* A10->DQS# */ \
191 (7 << 7) | /* OCD program */ \
192 (0 << 6) | /* Rtt1 */ \
193 (0 << 3) | /* posted CAS# */ \
194 (1 << 2) | /* Rtt0 */ \
195 (0 << 1) | /* ODS */ \
196 (0 << 0) /* DLL */ \
197 )
198
199/*
200 * Backward compatible definitions,
201 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
202 */
203#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
204#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
205#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
206#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
207
208/* DDR Priority Manager Configuration */
209#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
210#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
211#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
212#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
213#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
214#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
215#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
216#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
217#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
218#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
219#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
220#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
221#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
222#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
223#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
224#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
225#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
226#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
227#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
228#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
229#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
230#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
231#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
232
233/*
234 * NOR FLASH on the Local Bus
235 */
236#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
237#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
238#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
239#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */
240
241#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
242#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
243#define CONFIG_SYS_FLASH_BANKS_LIST { \
244 CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
245 }
246#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
247
248#undef CONFIG_SYS_FLASH_CHECKSUM
249#define CONFIG_SYS_FLASH_PROTECTION
250
251/*
252 * SRAM support
253 */
254#define CONFIG_SYS_SRAM_BASE 0x30000000
255#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
256
257/*
258 * CS related parameters
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000259 */
260/* CS0 Flash */
261#define CONFIG_SYS_CS0_CFG 0x00031110
262#define CONFIG_SYS_CS0_START 0xFC000000
263#define CONFIG_SYS_CS0_SIZE 0x04000000
264/* CS1 FRAM */
265#define CONFIG_SYS_CS1_CFG 0x00011000
266#define CONFIG_SYS_CS1_START 0xE0000000
267#define CONFIG_SYS_CS1_SIZE 0x00010000
268/* CS2 AS-i 1 */
269#define CONFIG_SYS_CS2_CFG 0x00009100
270#define CONFIG_SYS_CS2_START 0xE0100000
271#define CONFIG_SYS_CS2_SIZE 0x00080000
272/* CS3 netX */
273#define CONFIG_SYS_CS3_CFG 0x000A1140
274#define CONFIG_SYS_CS3_START 0xE0300000
275#define CONFIG_SYS_CS3_SIZE 0x00020000
276/* CS5 safety */
277#define CONFIG_SYS_CS5_CFG 0x0011F000
278#define CONFIG_SYS_CS5_START 0xE0400000
279#define CONFIG_SYS_CS5_SIZE 0x00010000
280/* CS6 AS-i 2 */
281#define CONFIG_SYS_CS6_CFG 0x00009100
282#define CONFIG_SYS_CS6_START 0xE0200000
283#define CONFIG_SYS_CS6_SIZE 0x00080000
284
285/* Don't use alternative CS timing for any CS */
286#define CONFIG_SYS_CS_ALETIMING 0x00000000
287#define CONFIG_SYS_CS_BURST 0x00000000
288#define CONFIG_SYS_CS_DEADCYCLE 0x00000020
289#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020
290
291/* Use SRAM for initial stack */
292#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
293#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
294
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000295#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900296 GENERATED_GBL_DATA_SIZE)
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000297#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
298
299#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
300#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
301
302#ifdef CONFIG_FSL_DIU_FB
303#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
304#else
305#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
306#endif
307
308/*
309 * Serial Port
310 */
311#define CONFIG_CONS_INDEX 1
312
313/*
314 * Serial console configuration
315 */
316#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
317#define CONFIG_SYS_PSC3
318#if CONFIG_PSC_CONSOLE != 3
319#error CONFIG_PSC_CONSOLE must be 3
320#endif
321
322#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000323
324#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
325#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
326#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
327#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
328
329/*
330 * Clocks in use
331 */
332#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
333 CLOCK_SCCR1_LPC_EN | \
334 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
335 CLOCK_SCCR1_PSC_EN(7) | \
336 CLOCK_SCCR1_PSCFIFO_EN | \
337 CLOCK_SCCR1_DDR_EN | \
338 CLOCK_SCCR1_FEC_EN | \
339 CLOCK_SCCR1_TPR_EN)
340
341#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
342 CLOCK_SCCR2_SPDIF_EN | \
343 CLOCK_SCCR2_DIU_EN | \
344 CLOCK_SCCR2_I2C_EN)
345
346
347#define CONFIG_CMDLINE_EDITING 1 /* command line history */
348
349/* I2C */
350#define CONFIG_HARD_I2C /* I2C with hardware support */
351#define CONFIG_I2C_MULTI_BUS
352
353/* I2C speed and slave address */
354#define CONFIG_SYS_I2C_SPEED 100000
355#define CONFIG_SYS_I2C_SLAVE 0x7F
356
357/*
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000358 * IIM - IC Identification Module
359 */
360#undef CONFIG_FSL_IIM
361
362/*
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000363 * EEPROM configuration for Atmel AT24C01:
364 * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
365 */
366#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
367#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
368#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30
369#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
370
371/*
372 * Ethernet configuration
373 */
374#define CONFIG_MPC512x_FEC 1
375#define CONFIG_NET_MULTI
376#define CONFIG_PHY_ADDR 0x1F
377#define CONFIG_MII 1 /* MII PHY management */
378#define CONFIG_FEC_AN_TIMEOUT 1
379#define CONFIG_HAS_ETH0
380
381/*
382 * Environment
383 */
384#define CONFIG_ENV_IS_IN_FLASH 1
385/* This has to be a multiple of the flash sector size */
386#define CONFIG_ENV_ADDR 0xFFF40000
387#define CONFIG_ENV_SIZE 0x2000
388#define CONFIG_ENV_SECT_SIZE 0x20000
389
390/* Address and size of Redundant Environment Sector */
391#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
392 CONFIG_ENV_SECT_SIZE)
393#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
394
395#define CONFIG_LOADS_ECHO 1
396#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
397
398#include <config_cmd_default.h>
399
400#define CONFIG_CMD_ASKENV
401#define CONFIG_CMD_DHCP
402#define CONFIG_CMD_EEPROM
403#undef CONFIG_CMD_FUSE
404#define CONFIG_CMD_I2C
405#undef CONFIG_CMD_IDE
406#undef CONFIG_CMD_EXT2
407#define CONFIG_CMD_JFFS2
408#define CONFIG_CMD_MII
409#define CONFIG_CMD_NFS
410#define CONFIG_CMD_PING
411#define CONFIG_CMD_REGINFO
412
413#if defined(CONFIG_PCI)
414#define CONFIG_CMD_PCI
415#endif
416
417#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
418#define CONFIG_DOS_PARTITION
419#define CONFIG_MAC_PARTITION
420#define CONFIG_ISO_PARTITION
421#endif /* defined(CONFIG_CMD_IDE) */
422
423/*
424 * Miscellaneous configurable options
425 */
426#define CONFIG_SYS_LONGHELP /* undef to save memory */
427#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
428#define CONFIG_SYS_PROMPT "ac14xx> " /* Monitor Command Prompt */
429
430#ifdef CONFIG_CMD_KGDB
431# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
432#else
433# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
434#endif
435
436/* Print Buffer Size */
437#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
438 sizeof(CONFIG_SYS_PROMPT) + 16)
439/* max number of command args */
440#define CONFIG_SYS_MAXARGS 32
441/* Boot Argument Buffer Size */
442#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
443
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000444/*
445 * For booting Linux, the board info and command line data
446 * have to be in the first 8 MB of memory, since this is
447 * the maximum mapped by the Linux kernel during initialization.
448 */
449#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
450
451/* Cache Configuration */
452#define CONFIG_SYS_DCACHE_SIZE 32768
453#define CONFIG_SYS_CACHELINE_SIZE 32
454#ifdef CONFIG_CMD_KGDB
455#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
456#endif
457
458#define CONFIG_SYS_HID0_INIT 0x000000000
459#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
460 HID0_ICE)
461#define CONFIG_SYS_HID2 HID2_HBE
462
463#define CONFIG_HIGH_BATS 1 /* High BATs supported */
464
465/*
466 * Internal Definitions
467 *
468 * Boot Flags
469 */
470#define BOOTFLAG_COLD 0x01
471#define BOOTFLAG_WARM 0x02
472
473#ifdef CONFIG_CMD_KGDB
474#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000475#endif
476
477/*
478 * Environment Configuration
479 */
480#define CONFIG_ENV_OVERWRITE
481#define CONFIG_TIMESTAMP
482
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000483/* default load addr for tftp and bootm */
484#define CONFIG_LOADADDR 400000
485
486#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
487
Gerhard Sittigb5992e72013-06-05 14:51:06 +0200488/* the builtin environment and standard greeting */
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000489#define CONFIG_PREBOOT "echo;" \
490 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
491 "echo"
492
493#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200494 "muster_nr=-00\0" \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000495 "fromram=run ramargs addip addtty; " \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200496 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
497 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
498 "tftp ${ramdisk_addr_r} ac14xx/uFS${muster_nr}; " \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000499 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
500 "fromnfs=run nfsargs addip addtty; " \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200501 "tftp ${fdt_addr_r} ac14xx/ac14xx.dtb${muster_nr}; " \
502 "tftp ${kernel_addr_r} ac14xx/uImage${muster_nr}; " \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000503 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
504 "fromflash=run nfsargs addip addtty; " \
505 "bootm fc020000 - fc000000\0" \
506 "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \
507 "recovery=run mtdargsrec addip addtty; " \
508 "bootm ffd20000 - ffee0000\0" \
509 "production=run ramargs addip addtty; " \
510 "bootm fc020000 fc400000 fc000000\0" \
511 "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \
512 "prodmtd=run mtdargs addip addtty; " \
513 "bootm fc020000 - fc000000\0" \
514 ""
515
516#define CONFIG_EXTRA_ENV_SETTINGS \
517 "u-boot_addr_r=200000\0" \
518 "kernel_addr_r=600000\0" \
519 "fdt_addr_r=a00000\0" \
520 "ramdisk_addr_r=b00000\0" \
521 "u-boot_addr=FFF00000\0" \
522 "kernel_addr=FC020000\0" \
523 "fdt_addr=FC000000\0" \
524 "ramdisk_addr=FC400000\0" \
525 "verify=n\0" \
526 "ramdiskfile=ac14xx/uRamdisk\0" \
527 "u-boot=ac14xx/u-boot.bin\0" \
528 "bootfile=ac14xx/uImage\0" \
529 "fdtfile=ac14xx/ac14xx.dtb\0" \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000530 "netdev=eth0\0" \
531 "consdev=ttyPSC0\0" \
532 "hostname=ac14xx\0" \
533 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200534 "nfsroot=${serverip}:${rootpath}${muster_nr}\0" \
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000535 "ramargs=setenv bootargs root=/dev/ram rw\0" \
536 "addip=setenv bootargs ${bootargs} " \
537 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
538 ":${hostname}:${netdev}:off panic=1\0" \
539 "addtty=setenv bootargs ${bootargs} " \
540 "console=${consdev},${baudrate}\0" \
541 "flash_nfs=run nfsargs addip addtty;" \
542 "bootm ${kernel_addr} - ${fdt_addr}\0" \
543 "flash_self=run ramargs addip addtty;" \
544 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
545 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
546 "tftp ${fdt_addr_r} ${fdtfile};" \
547 "run nfsargs addip addtty;" \
548 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
549 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
550 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
551 "tftp ${fdt_addr_r} ${fdtfile};" \
552 "run ramargs addip addtty;" \
553 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
554 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
555 "update=protect off ${u-boot_addr} +${filesize};" \
556 "era ${u-boot_addr} +${filesize};" \
557 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
558 CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
559 "upd=run load update\0" \
560 ""
561
562#define CONFIG_BOOTCOMMAND "run production"
563
Gerhard Sittig6c5001d2013-06-05 14:51:11 +0200564#define CONFIG_ARP_TIMEOUT 200UL
565
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000566#define CONFIG_FIT 1
567#define CONFIG_OF_LIBFDT 1
568#define CONFIG_OF_BOARD_SETUP 1
569#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
570
571#define OF_CPU "PowerPC,5121@0"
572#define OF_SOC_COMPAT "fsl,mpc5121-immr"
573#define OF_TBCLK (bd->bi_busfreq / 4)
574#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
575
576#endif /* __CONFIG_H */