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Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +01001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +01007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020012
Andreas Bießmann09d623c2011-04-18 04:12:39 +000013#define CONFIG_AT32AP
14#define CONFIG_AT32AP7000
15#define CONFIG_ATSTK1006
16#define CONFIG_ATSTK1000
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010017
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010018
19/*
20 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
21 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
22 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010024 */
Andreas Bießmann09d623c2011-04-18 04:12:39 +000025#define CONFIG_PLL
26#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_OSC0_HZ 20000000
28#define CONFIG_SYS_PLL0_DIV 1
29#define CONFIG_SYS_PLL0_MUL 7
30#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010031/*
32 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010034 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020035#define CONFIG_SYS_CLKDIV_CPU 0
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010036/*
37 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010039 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_CLKDIV_HSB 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010041/*
42 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010044 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_CLKDIV_PBA 2
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010046/*
47 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010049 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010051
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070052/* Reserve VM regions for SDRAM and NOR flash */
53#define CONFIG_SYS_NR_VM_REGIONS 2
54
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010055/*
56 * The PLLOPT register controls the PLL like this:
57 * icp = PLLOPT<2>
58 * ivco = PLLOPT<1:0>
59 *
60 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
61 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010063
Andreas Bießmannf4278b72010-11-04 23:15:31 +000064#define CONFIG_USART_BASE ATMEL_BASE_USART1
65#define CONFIG_USART_ID 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010066
67/* User serviceable stuff */
Andreas Bießmann09d623c2011-04-18 04:12:39 +000068#define CONFIG_DOS_PARTITION
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010069
Andreas Bießmann09d623c2011-04-18 04:12:39 +000070#define CONFIG_CMDLINE_TAG
71#define CONFIG_SETUP_MEMORY_TAGS
72#define CONFIG_INITRD_TAG
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010073
74#define CONFIG_STACKSIZE (2048)
75
76#define CONFIG_BAUDRATE 115200
77#define CONFIG_BOOTARGS \
78 "console=ttyS0 root=mtd3 fbmem=2400k"
79
80#define CONFIG_BOOTCOMMAND \
81 "fsload; bootm $(fileaddr)"
82
83/*
84 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
85 * data on the serial line may interrupt the boot sequence.
86 */
87#define CONFIG_BOOTDELAY 1
Andreas Bießmann09d623c2011-04-18 04:12:39 +000088#define CONFIG_AUTOBOOT
89#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +020090#define CONFIG_AUTOBOOT_PROMPT \
91 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010092#define CONFIG_AUTOBOOT_DELAY_STR "d"
93#define CONFIG_AUTOBOOT_STOP_STR " "
94
95/*
96 * After booting the board for the first time, new ethernet addresses
97 * should be generated and assigned to the environment variables
98 * "ethaddr" and "eth1addr". This is normally done during production.
99 */
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000100#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100101
102/*
103 * BOOTP options
104 */
105#define CONFIG_BOOTP_SUBNETMASK
106#define CONFIG_BOOTP_GATEWAY
107
108
109/*
110 * Command line configuration.
111 */
112#include <config_cmd_default.h>
113
114#define CONFIG_CMD_ASKENV
115#define CONFIG_CMD_DHCP
116#define CONFIG_CMD_EXT2
117#define CONFIG_CMD_FAT
118#define CONFIG_CMD_JFFS2
119#define CONFIG_CMD_MMC
120
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100121#undef CONFIG_CMD_FPGA
122#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200123#undef CONFIG_CMD_SOURCE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100124#undef CONFIG_CMD_XIMG
125
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000126#define CONFIG_ATMEL_USART
127#define CONFIG_MACB
128#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000130#define CONFIG_SYS_HSDRAMC
131#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200132#define CONFIG_GENERIC_ATMEL_MCI
133#define CONFIG_GENERIC_MMC
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_DCACHE_LINESZ 32
136#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100137
138#define CONFIG_NR_DRAM_BANKS 1
139
Andreas Bießmann22178652011-06-28 04:15:58 +0000140#define CONFIG_SYS_FLASH_CFI
141#define CONFIG_FLASH_CFI_DRIVER
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BASE 0x00000000
144#define CONFIG_SYS_FLASH_SIZE 0x800000
145#define CONFIG_SYS_MAX_FLASH_BANKS 1
146#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann47293c12011-04-18 04:12:44 +0000149#define CONFIG_SYS_TEXT_BASE 0x00000000
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
152#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
153#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100154
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000155#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200156#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_MALLOC_LEN (256*1024)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100162
163/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
165#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100166
167/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_PROMPT "U-Boot> "
169#define CONFIG_SYS_CBSIZE 256
170#define CONFIG_SYS_MAXARGS 16
171#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000172#define CONFIG_SYS_LONGHELP
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
175#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000)
176#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100177
178#endif /* __CONFIG_H */