blob: 9703c840b7ba956662145e61031e0b7137076645 [file] [log] [blame]
Vladimir Barinov60c04672015-02-14 01:06:13 +03001/*
2 * include/configs/porter.h
3 * This file is Porter board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __PORTER_H
12#define __PORTER_H
13
14#undef DEBUG
15#define CONFIG_R8A7791
16#define CONFIG_RMOBILE_BOARD_STRING "Porter"
17
18#include "rcar-gen2-common.h"
19
20#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
21#define CONFIG_SYS_TEXT_BASE 0x70000000
22#else
23#define CONFIG_SYS_TEXT_BASE 0xE6304000
24#endif
25
26#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
27#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
28#else
29#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
30#endif
31#define STACK_AREA_SIZE 0xC000
32#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
36#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
39
40/* SCIF */
41#define CONFIG_SCIF_CONSOLE
42
43/* FLASH */
44#define CONFIG_SPI
45#define CONFIG_SPI_FLASH_BAR
46#define CONFIG_SH_QSPI
47#define CONFIG_SPI_FLASH
48#define CONFIG_SPI_FLASH_SPANSION
49#define CONFIG_SPI_FLASH_QUAD
50#define CONFIG_SYS_NO_FLASH
51
52/* SH Ether */
53#define CONFIG_NET_MULTI
54#define CONFIG_SH_ETHER
55#define CONFIG_SH_ETHER_USE_PORT 0
56#define CONFIG_SH_ETHER_PHY_ADDR 0x1
57#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
58#define CONFIG_SH_ETHER_CACHE_WRITEBACK
59#define CONFIG_SH_ETHER_CACHE_INVALIDATE
60#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
61#define CONFIG_PHYLIB
62#define CONFIG_PHY_MICREL
63#define CONFIG_BITBANGMII
64#define CONFIG_BITBANGMII_MULTI
65
66/* Board Clock */
67#define RMOBILE_XTAL_CLK 20000000u
68#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
69#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
70#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
71#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
72
73#define CONFIG_SYS_TMU_CLK_DIV 4
74
75/* i2c */
76#define CONFIG_CMD_I2C
77#define CONFIG_SYS_I2C
78#define CONFIG_SYS_I2C_SH
79#define CONFIG_SYS_I2C_SLAVE 0x7F
80#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
81#define CONFIG_SYS_I2C_SH_SPEED0 400000
82#define CONFIG_SYS_I2C_SH_SPEED1 400000
83#define CONFIG_SYS_I2C_SH_SPEED2 400000
84#define CONFIG_SH_I2C_DATA_HIGH 4
85#define CONFIG_SH_I2C_DATA_LOW 5
86#define CONFIG_SH_I2C_CLOCK 10000000
87
88#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
89
90/* USB */
91#define CONFIG_USB_EHCI
92#define CONFIG_USB_EHCI_RMOBILE
93#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
94#define CONFIG_USB_STORAGE
95
96/* SD */
97#define CONFIG_MMC
98#define CONFIG_CMD_MMC
99#define CONFIG_GENERIC_MMC
100#define CONFIG_SH_SDHI_FREQ 97500000
101
102/* Module stop status bits */
103/* INTC-RT */
104#define CONFIG_SMSTP0_ENA 0x00400000
105/* MSIF */
106#define CONFIG_SMSTP2_ENA 0x00002000
107/* INTC-SYS, IRQC */
108#define CONFIG_SMSTP4_ENA 0x00000180
109/* SCIF0 */
110#define CONFIG_SMSTP7_ENA 0x00200000
111
112#endif /* __PORTER_H */