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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09002/*
3 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4 * Copyright (C) 2012 Renesas Solutions Corp.
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09005 */
6
7#ifndef __KZM9G_H
8#define __KZM9G_H
9
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090010#define CONFIG_SH73A0
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090011
12#include <asm/arch/rmobile.h>
13
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090014/* MEMORY */
15#define KZM_SDRAM_BASE (0x40000000)
16#define PHYS_SDRAM KZM_SDRAM_BASE
17#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090018
19/* NOR Flash */
20#define KZM_FLASH_BASE (0x00000000)
21#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090022
23/* prompt */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090024#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
25
26/* SCIF */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090027
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090028#undef CONFIG_SYS_LOADS_BAUD_CHANGE
29
30#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
31#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
32#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
Tetsuyuki Kobayashi9415cf92012-07-05 01:43:44 +000033#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
34#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
35#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090036
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090037#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
38
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090039#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
40
41/* FLASH */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090042#undef CONFIG_SYS_FLASH_QUIET_TEST
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090043#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090044
45/* Timeout for Flash erase operations (in ms) */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090046/* Timeout for Flash write operations (in ms) */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090047/* Timeout for Flash set sector lock bit operations (in ms) */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090048/* Timeout for Flash clear lock bit operations (in ms) */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090049
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090050/* GPIO / PFC */
51#define CONFIG_SH_GPIO_PFC
52
53/* Clock */
Nobuhiro Iwamatsueae6c8a2012-08-03 13:56:52 +090054#define CONFIG_GLOBAL_TIMER
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090055#define CONFIG_SYS_CPU_CLK (1196000000)
56#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090057
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090058#endif /* __KZM9G_H */