blob: 81ffb8ed7904fae2499c2525330b54bb6dd42942 [file] [log] [blame]
Michael Brandtd3d64272011-04-19 10:42:41 +00001/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Basic U-Boot I2C interface for STn8500/DB8500
5 * Author: Michael Brandt <Michael.Brandt@stericsson.com> for ST-Ericsson
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Michael Brandtd3d64272011-04-19 10:42:41 +00008 */
9
10/*
11 * Only 7-bit I2C device addresses are supported.
12 */
13
14#include <common.h>
15#include <i2c.h>
16
17#include "u8500_i2c.h"
18#include <asm/io.h>
19#include <asm/arch/clock.h>
20
21#define U8500_I2C_ENDAD_COUNTER (CONFIG_SYS_HZ/100) /* I2C bus timeout */
22#define U8500_I2C_FIFO_FLUSH_COUNTER 500000 /* flush "timeout" */
23#define U8500_I2C_SCL_FREQ 100000 /* I2C bus clock freq */
24#define U8500_I2C_INPUT_FREQ 48000000 /* Input clock freq */
25#define TX_FIFO_THRESHOLD 0x4
26#define RX_FIFO_THRESHOLD 0x4
27#define SLAVE_SETUP_TIME 14 /* Slave data setup time, 250ns for 48MHz i2c_clk */
28
29#define WRITE_FIELD(var, mask, shift, value) \
30 (var = ((var & ~(mask)) | ((value) << (shift))))
31
32static unsigned int bus_initialized[CONFIG_SYS_U8500_I2C_BUS_MAX];
33static unsigned int i2c_bus_num;
34static unsigned int i2c_bus_speed[] = {
35 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED,
36 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED
37};
38static struct u8500_i2c_regs *i2c_dev[] = {
39 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C0_BASE,
40 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C1_BASE,
41 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C2_BASE,
42 (struct u8500_i2c_regs *)CONFIG_SYS_U8500_I2C3_BASE,
43};
44
45static struct {
46 int periph;
47 int pcken;
48 int kcken;
49} i2c_clock_bits[] = {
50 {3, 3, 3}, /* I2C0 */
51 {1, 2, 2}, /* I2C1 */
52 {1, 6, 6}, /* I2C2 */
53 {2, 0, 0}, /* I2C3 */
54};
55
56static void i2c_set_bit(void *reg, u32 mask)
57{
58 writel(readl(reg) | mask, reg);
59}
60
61static void i2c_clr_bit(void *reg, u32 mask)
62{
63 writel(readl(reg) & ~mask, reg);
64}
65
66static void i2c_write_field(void *reg, u32 mask, uint shift, u32 value)
67{
68 writel((readl(reg) & ~mask) | (value << shift), reg);
69}
70
71static int __i2c_set_bus_speed(unsigned int speed)
72{
73 u32 value;
74 struct u8500_i2c_regs *i2c_regs;
75
76 i2c_regs = i2c_dev[i2c_bus_num];
77
78 /* Select standard (100 kbps) speed mode */
79 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_SM,
80 U8500_I2C_CR_SHIFT_SM, 0x0);
81
82 /*
83 * Set the Baud Rate Counter 2 value
84 * Baud rate (standard) = fi2cclk / ( (BRCNT2 x 2) + Foncycle )
85 * Foncycle = 0 (no digital filtering)
86 */
87 value = (u32) (U8500_I2C_INPUT_FREQ / (speed * 2));
88 i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT2,
89 U8500_I2C_BRCR_SHIFT_BRCNT2, value);
90
91 /* ensure that BRCNT value is zero */
92 i2c_write_field(&i2c_regs->brcr, U8500_I2C_BRCR_BRCNT1,
93 U8500_I2C_BRCR_SHIFT_BRCNT1, 0);
94
95 return U8500_I2C_INPUT_FREQ/(value * 2);
96}
97
98/*
99 * i2c_init - initialize the i2c bus
100 *
101 * speed: bus speed (in HZ)
102 * slaveaddr: address of device in slave mode
103 *
104 * Slave mode is not implemented.
105 */
106void i2c_init(int speed, int slaveaddr)
107{
108 struct u8500_i2c_regs *i2c_regs;
109
110 debug("i2c_init bus %d, speed %d\n", i2c_bus_num, speed);
111
112 u8500_clock_enable(i2c_clock_bits[i2c_bus_num].periph,
113 i2c_clock_bits[i2c_bus_num].pcken,
114 i2c_clock_bits[i2c_bus_num].kcken);
115
116 i2c_regs = i2c_dev[i2c_bus_num];
117
118 /* Disable the controller */
119 i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
120
121 /* Clear registers */
122 writel(0, &i2c_regs->cr);
123 writel(0, &i2c_regs->scr);
124 writel(0, &i2c_regs->hsmcr);
125 writel(0, &i2c_regs->tftr);
126 writel(0, &i2c_regs->rftr);
127 writel(0, &i2c_regs->dmar);
128
129 i2c_bus_speed[i2c_bus_num] = __i2c_set_bus_speed(speed);
130
131 /*
132 * Set our own address.
133 * Set slave address mode to 7 bit addressing mode
134 */
135 i2c_clr_bit(&i2c_regs->cr, U8500_I2C_CR_SAM);
136 i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_ADDR,
137 U8500_I2C_SCR_SHIFT_ADDR, slaveaddr);
138 /* Slave Data Set up Time */
139 i2c_write_field(&i2c_regs->scr, U8500_I2C_SCR_DATA_SETUP_TIME,
140 U8500_I2C_SCR_SHIFT_DATA_SETUP_TIME, SLAVE_SETUP_TIME);
141
142 /* Disable the DMA sync logic */
143 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_DMA_SLE,
144 U8500_I2C_CR_SHIFT_DMA_SLE, 0);
145
146 /* Disable interrupts */
147 writel(0, &i2c_regs->imscr);
148
149 /* Configure bus master mode */
150 i2c_write_field(&i2c_regs->cr, U8500_I2C_CR_OM, U8500_I2C_CR_SHIFT_OM,
151 U8500_I2C_BUS_MASTER_MODE);
152 /* Set FIFO threshold values */
153 writel(TX_FIFO_THRESHOLD, &i2c_regs->tftr);
154 writel(RX_FIFO_THRESHOLD, &i2c_regs->rftr);
155
156 /* Enable the I2C Controller */
157 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_PE);
158
159 bus_initialized[i2c_bus_num] = 1;
160}
161
162
163/*
164 * loop_till_bit_clear - polls on a bit till it clears
165 * ioreg: register where you want to check status
166 * mask: bit mask for the bit you wish to check
167 * timeout: timeout in ticks/s
168 */
169static int loop_till_bit_clear(void *io_reg, u32 mask, unsigned long timeout)
170{
171 unsigned long timebase = get_timer(0);
172
173 do {
174 if ((readl(io_reg) & mask) == 0x0UL)
175 return 0;
176 } while (get_timer(timebase) < timeout);
177
178 debug("loop_till_bit_clear timed out\n");
179 return -1;
180}
181
182/*
183 * loop_till_bit_set - polls on a bit till it is set.
184 * ioreg: register where you want to check status
185 * mask: bit mask for the bit you wish to check
186 * timeout: timeout in ticks/s
187 */
188static int loop_till_bit_set(void *io_reg, u32 mask, unsigned long timeout)
189{
190 unsigned long timebase = get_timer(0);
191
192 do {
193 if ((readl(io_reg) & mask) != 0x0UL)
194 return 0;
195 } while (get_timer(timebase) < timeout);
196
197 debug("loop_till_bit_set timed out\n");
198 return -1;
199}
200
201/*
202 * flush_fifo - flush the I2C TX and RX FIFOs
203 */
204static void flush_fifo(struct u8500_i2c_regs *i2c_regs)
205{
206 int counter = U8500_I2C_FIFO_FLUSH_COUNTER;
207
208 /* Flush Tx FIFO */
209 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FTX);
210 /* Flush Rx FIFO */
211 i2c_set_bit(&i2c_regs->cr, U8500_I2C_CR_FRX);
212 while (counter--) {
213 if (!(readl(&i2c_regs->cr) &
214 (U8500_I2C_CR_FTX | U8500_I2C_CR_FRX)))
215 break;
216 }
217 return;
218}
219
220#ifdef DEBUG
221static void print_abort_reason(struct u8500_i2c_regs *i2c_regs)
222{
223 int cause;
224
225 printf("abort: risr %08x, sr %08x\n", i2c_regs->risr, i2c_regs->sr);
226 cause = (readl(&i2c_regs->sr) & U8500_I2C_SR_CAUSE) >>
227 U8500_I2C_SR_SHIFT_CAUSE;
228 switch (cause) {
229 case U8500_I2C_NACK_ADDR:
230 printf("No Ack received after Slave Address xmission\n");
231 break;
232 case U8500_I2C_NACK_DATA:
233 printf("Valid for MASTER_WRITE: No Ack received "
234 "during data phase\n");
235 break;
236 case U8500_I2C_ACK_MCODE:
237 printf("Master recv ack after xmission of master code"
238 "in hs mode\n");
239 break;
240 case U8500_I2C_ARB_LOST:
241 printf("Master Lost arbitration\n");
242 break;
243 case U8500_I2C_BERR_START:
244 printf("Slave restarts\n");
245 break;
246 case U8500_I2C_BERR_STOP:
247 printf("Slave reset\n");
248 break;
249 case U8500_I2C_OVFL:
250 printf("Overflow\n");
251 break;
252 default:
253 printf("Unknown error type\n");
254 }
255}
256#endif
257
258/*
259 * i2c_abort - called when a I2C transaction failed
260 */
261static void i2c_abort(struct u8500_i2c_regs *i2c_regs)
262{
263#ifdef DEBUG
264 print_abort_reason(i2c_regs);
265#endif
266 /* flush RX and TX fifos */
267 flush_fifo(i2c_regs);
268
269 /* Acknowledge the Master Transaction Done */
270 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
271
272 /* Acknowledge the Master Transaction Done Without Stop */
273 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
274
275 i2c_init(i2c_bus_speed[i2c_bus_num], CONFIG_SYS_I2C_SLAVE);
276}
277
278/*
279 * write addr, alias index, to I2C bus.
280 */
281static int i2c_write_addr(struct u8500_i2c_regs *i2c_regs, uint addr, int alen)
282{
283 while (alen--) {
284 /* Wait until the Tx Fifo is not full */
285 if (loop_till_bit_clear((void *)&i2c_regs->risr,
286 U8500_I2C_INT_TXFF,
287 U8500_I2C_ENDAD_COUNTER)) {
288 i2c_abort(i2c_regs);
289 return -1;
290 }
291
292 /* MSB first */
293 writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->tfr);
294 }
295
296 return 0;
297}
298
299/*
300 * Internal simplified read function:
301 * i2c_regs: Pointer to I2C registers for current bus
302 * chip: I2C chip address, range 0..127
303 * addr: Memory (register) address within the chip
304 * alen: Number of bytes to use for addr (typically 1, 2 for larger
305 * memories, 0 for register type devices with only one register)
306 * value: Where to put the data
307 *
308 * Returns: 0 on success, not 0 on failure
309 */
310static int i2c_read_byte(struct u8500_i2c_regs *i2c_regs, uchar chip,
311 uint addr, int alen, uchar *value)
312{
313 u32 mcr = 0;
314
315 /* Set the address mode to 7 bit */
316 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
317
318 /* Store the slave address in the master control register */
319 WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
320
321 if (alen != 0) {
322 /* Master write operation */
323 mcr &= ~(U8500_I2C_MCR_OP);
324
325 /* Configure the Frame length to one byte */
326 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH,
327 U8500_I2C_MCR_SHIFT_LENGTH, 1);
328
329 /* Repeated start, no stop */
330 mcr &= ~(U8500_I2C_MCR_STOP);
331
332 /* Write Master Control Register */
333 writel(mcr, &i2c_regs->mcr);
334
335 /* send addr/index */
336 if (i2c_write_addr(i2c_regs, addr, alen) != 0)
337 return -1;
338
339 /* Check for the Master Transaction Done Without Stop */
340 if (loop_till_bit_set((void *)&i2c_regs->risr,
341 U8500_I2C_INT_MTDWS,
342 U8500_I2C_ENDAD_COUNTER)) {
343 return -1;
344 }
345
346 /* Acknowledge the Master Transaction Done Without Stop */
347 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
348 }
349
350 /* Master control configuration for read operation */
351 mcr |= U8500_I2C_MCR_OP;
352
353 /* Configure the STOP condition, we read only one byte */
354 mcr |= U8500_I2C_MCR_STOP;
355
356 /* Set the frame length to one byte, we support only 1 byte reads */
357 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
358
359 i2c_write_field(&i2c_regs->mcr, U8500_I2C_MCR_LENGTH_STOP_OP,
360 U8500_I2C_MCR_SHIFT_LENGTH_STOP_OP, mcr);
361
362 /*
363 * receive_data_polling
364 */
365
366 /* Wait until the Rx FIFO is not empty */
367 if (loop_till_bit_clear((void *)&i2c_regs->risr,
368 U8500_I2C_INT_RXFE,
369 U8500_I2C_ENDAD_COUNTER))
370 return -1;
371
372 /* Read the data byte from Rx FIFO */
373 *value = readb(&i2c_regs->rfr);
374
375 /* Wait until the work is done */
376 if (loop_till_bit_set((void *)&i2c_regs->risr, U8500_I2C_INT_MTD,
377 U8500_I2C_ENDAD_COUNTER))
378 return -1;
379
380 /* Acknowledge the Master Transaction Done */
381 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
382
383 /* If MTD is set, Master Transaction Done Without Stop is set too */
384 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
385
386 return 0;
387}
388
389/*
390 * Internal simplified write function:
391 * i2c_regs: Pointer to I2C registers for current bus
392 * chip: I2C chip address, range 0..127
393 * addr: Memory (register) address within the chip
394 * alen: Number of bytes to use for addr (typically 1, 2 for larger
395 * memories, 0 for register type devices with only one register)
396 * data: Where to read the data
397 * len: How many bytes to write
398 *
399 * Returns: 0 on success, not 0 on failure
400 */
401static int __i2c_write(struct u8500_i2c_regs *i2c_regs, u8 chip, uint addr,
402 int alen, u8 *data, int len)
403{
404 int i;
405 u32 mcr = 0;
406
407 /* Set the address mode to 7 bit */
408 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
409
410 /* Store the slave address in the master control register */
411 WRITE_FIELD(mcr, U8500_I2C_MCR_A7, U8500_I2C_MCR_SHIFT_A7, chip);
412
413 /* Write operation */
414 mcr &= ~(U8500_I2C_MCR_OP);
415
416 /* Current transaction is terminated by STOP condition */
417 mcr |= U8500_I2C_MCR_STOP;
418
419 /* Frame length: addr byte + len */
420 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH,
421 (alen + len));
422
423 /* Write MCR register */
424 writel(mcr, &i2c_regs->mcr);
425
426 if (i2c_write_addr(i2c_regs, addr, alen) != 0)
427 return -1;
428
429 for (i = 0; i < len; i++) {
430 /* Wait until the Tx FIFO is not full */
431 if (loop_till_bit_clear((void *)&i2c_regs->risr,
432 U8500_I2C_INT_TXFF,
433 U8500_I2C_ENDAD_COUNTER))
434 return -1;
435
436 /* it is a 32 bit register with upper 24 reserved R/O */
437 writeb(data[i], &i2c_regs->tfr);
438 }
439
440 /* Check for Master Transaction Done */
441 if (loop_till_bit_set((void *)&i2c_regs->risr,
442 U8500_I2C_INT_MTD,
443 U8500_I2C_ENDAD_COUNTER)) {
444 printf("i2c_write_byte error2: risr %08x\n",
445 i2c_regs->risr);
446 return -1;
447 }
448
449 /* Acknowledge Master Transaction Done */
450 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
451
452 /* Acknowledge Master Transaction Done Without Stop */
453 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
454
455 return 0;
456}
457
458/*
459 * Probe the given I2C chip address. Returns 0 if a chip responded,
460 * not 0 on failure.
461 */
462int i2c_probe(uchar chip)
463{
464 u32 mcr = 0;
465 struct u8500_i2c_regs *i2c_regs;
466
467 if (chip == CONFIG_SYS_I2C_SLAVE)
468 return 1;
469
470 i2c_regs = i2c_dev[i2c_bus_num];
471
472 /* Set the address mode to 7 bit */
473 WRITE_FIELD(mcr, U8500_I2C_MCR_AM, U8500_I2C_MCR_SHIFT_AM, 1);
474
475 /* Store the slave address in the master control register */
476 WRITE_FIELD(mcr, U8500_I2C_MCR_A10, U8500_I2C_MCR_SHIFT_A7, chip);
477
478 /* Read operation */
479 mcr |= U8500_I2C_MCR_OP;
480
481 /* Set the frame length to one byte */
482 WRITE_FIELD(mcr, U8500_I2C_MCR_LENGTH, U8500_I2C_MCR_SHIFT_LENGTH, 1);
483
484 /* Current transaction is terminated by STOP condition */
485 mcr |= U8500_I2C_MCR_STOP;
486
487 /* Write MCR register */
488 writel(mcr, &i2c_regs->mcr);
489
490 /* Wait until the Rx Fifo is not empty */
491 if (loop_till_bit_clear((void *)&i2c_regs->risr,
492 U8500_I2C_INT_RXFE,
493 U8500_I2C_ENDAD_COUNTER)) {
494 i2c_abort(i2c_regs);
495 return -1;
496 }
497
498 flush_fifo(i2c_regs);
499
500 /* Acknowledge the Master Transaction Done */
501 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTD);
502
503 /* Acknowledge the Master Transaction Done Without Stop */
504 i2c_set_bit(&i2c_regs->icr, U8500_I2C_INT_MTDWS);
505
506 return 0;
507}
508
509/*
510 * Read/Write interface:
511 * chip: I2C chip address, range 0..127
512 * addr: Memory (register) address within the chip
513 * alen: Number of bytes to use for addr (typically 1, 2 for larger
514 * memories, 0 for register type devices with only one
515 * register)
516 * buffer: Where to read/write the data
517 * len: How many bytes to read/write
518 *
519 * Returns: 0 on success, not 0 on failure
520 */
521int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
522{
523 int i;
524 int rc;
525 struct u8500_i2c_regs *i2c_regs;
526
527 if (alen > 2) {
528 debug("I2C read: addr len %d not supported\n", alen);
529 return 1;
530 }
531
532 i2c_regs = i2c_dev[i2c_bus_num];
533
534 for (i = 0; i < len; i++) {
535 rc = i2c_read_byte(i2c_regs, chip, addr + i, alen, &buffer[i]);
536 if (rc != 0) {
537 debug("I2C read: I/O error: %d\n", rc);
538 i2c_abort(i2c_regs);
539 return rc;
540 }
541 }
542
543 return 0;
544}
545
546int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
547{
548 int rc;
549 struct u8500_i2c_regs *i2c_regs;
550 i2c_regs = i2c_dev[i2c_bus_num];
551
552 rc = __i2c_write(i2c_regs, chip, addr, alen, buffer,
553 len);
554 if (rc != 0) {
555 debug("I2C write: I/O error\n");
556 i2c_abort(i2c_regs);
557 return rc;
558 }
559 return 0;
560}
561
562int i2c_set_bus_num(unsigned int bus)
563{
564 if (bus > ARRAY_SIZE(i2c_dev) - 1) {
565 debug("i2c_set_bus_num: only up to bus %d supported\n",
566 ARRAY_SIZE(i2c_dev)-1);
567 return -1;
568 }
569
570 i2c_bus_num = bus;
571
572 if (!bus_initialized[i2c_bus_num])
573 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
574
575 return 0;
576}
577
578int i2c_set_bus_speed(unsigned int speed)
579{
580
581 if (speed > U8500_I2C_MAX_STANDARD_SCL) {
582 debug("i2c_set_bus_speed: only up to %d supported\n",
583 U8500_I2C_MAX_STANDARD_SCL);
584 return -1;
585 }
586
587 /* sets as side effect i2c_bus_speed[i2c_bus_num] */
588 i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
589
590 return 0;
591}
592
593unsigned int i2c_get_bus_num(void)
594{
595 return i2c_bus_num;
596}
597
598unsigned int i2c_get_bus_speed(void)
599{
600 return i2c_bus_speed[i2c_bus_num];
601}