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Dirk Eibachab4c62c2009-07-27 08:49:48 +02001/*
2 * (C) Copyright 2009
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * Based on include/configs/canyonlands.h
6 * (C) Copyright 2008
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
Dirk Eibach4c188362009-09-09 12:36:07 +020026 * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center
Dirk Eibachab4c62c2009-07-27 08:49:48 +020027 */
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 */
34/*
Dirk Eibach4c188362009-09-09 12:36:07 +020035 * This config file is used for CompactCenter(codename intip) and DevCon-Center
Dirk Eibachab4c62c2009-07-27 08:49:48 +020036 */
37#define CONFIG_460EX 1 /* Specific PPC460EX */
38#ifdef CONFIG_DEVCONCENTER
39#define CONFIG_HOSTNAME devconcenter
Dirk Eibach15cc3852011-10-04 11:13:55 +020040#define CONFIG_IDENT_STRING " devconcenter 0.05"
Dirk Eibachab4c62c2009-07-27 08:49:48 +020041#else
Dirk Eibach4c188362009-09-09 12:36:07 +020042#define CONFIG_HOSTNAME intip
Dirk Eibach15cc3852011-10-04 11:13:55 +020043#define CONFIG_IDENT_STRING " intip 0.05"
Dirk Eibachab4c62c2009-07-27 08:49:48 +020044#endif
45#define CONFIG_440 1
46#define CONFIG_4xx 1 /* ... PPC4xx family */
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048#ifndef CONFIG_SYS_TEXT_BASE
49#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
50#endif
51
Dirk Eibachab4c62c2009-07-27 08:49:48 +020052/*
53 * Include common defines/options for all AMCC eval boards
54 */
55#include "amcc-common.h"
56
57#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
58
59#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
60#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
61#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
62#define CONFIG_BOARD_TYPES 1 /* support board types */
63#define CONFIG_FIT
64#define CFG_ALT_MEMTEST
65
Dirk Eibach55ac7192011-10-04 11:13:52 +020066#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
67#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
68#define CONFIG_AUTOBOOT_STOP_STR " "
69
Dirk Eibachab4c62c2009-07-27 08:49:48 +020070/*
71 * Base addresses -- Note these are effective addresses where the
72 * actual resources get mapped (not physical addresses)
73 */
74#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
75#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
76#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
77
78/* EBC stuff */
79#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
80#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */
81#define CONFIG_SYS_FLASH_SIZE (128 << 20)
82#else
83#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */
84#define CONFIG_SYS_FLASH_SIZE (64 << 20)
85#endif
86
87#define CONFIG_SYS_NVRAM_BASE 0xE0000000
88#define CONFIG_SYS_UART_BASE 0xE0100000
89#define CONFIG_SYS_IO_BASE 0xE0200000
90
91#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */
92#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
93#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */
94#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000
95#else
96#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
97#endif
98#define CONFIG_SYS_FLASH_BASE_PHYS \
99 (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \
100 | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
101
102#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
103#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
Wolfgang Denkbf560802010-09-10 23:04:05 +0200104#define CONFIG_SYS_SRAM_SIZE (256 << 10)
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200105#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
106
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200107#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */
108
109/*
110 * Initial RAM & stack pointer (placed in OCM)
111 */
112#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200113#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200114#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200115 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200116#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
117
118/*
119 * Serial Port
120 */
Stefan Roese550650d2010-09-20 16:05:31 +0200121#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200122
123/*
124 * Environment
125 */
126/*
127 * Define here the location of the environment variables (FLASH).
128 */
129#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
130#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
131
132/*
133 * FLASH related
134 */
135#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
136#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
137#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
138
139#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
140#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
141#ifdef CONFIG_DEVCONCENTER
142#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/
143#else
144#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
145#endif
146
147#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
148#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
149
150#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */
151#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
152
153#ifdef CONFIG_ENV_IS_IN_FLASH
154#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/
155#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
156#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
157
158/* Address and size of Redundant Environment Sector */
159#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
160#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
161#endif /* CONFIG_ENV_IS_IN_FLASH */
162
163/*
164 * DDR SDRAM
165 */
166
167#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
168
169#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
170#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
171#undef CONFIG_PPC4xx_DDR_METHOD_A
172
173/* DDR1/2 SDRAM Device Control Register Data Values */
174/* Memory Queue */
175#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800
176#define CONFIG_SYS_SDRAM_R1BAS 0x00000000
177#define CONFIG_SYS_SDRAM_R2BAS 0x00000000
178#define CONFIG_SYS_SDRAM_R3BAS 0x00000000
179#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
180#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
Dirk Eibach91d59902009-09-21 13:27:14 +0200181#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200182#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80
183#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
184
185/* SDRAM Controller */
186#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201
187#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
188#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
189#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
Dirk Eibach91d59902009-09-21 13:27:14 +0200190#define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200191#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
192#define CONFIG_SYS_SDRAM0_MODT0 0x00000000
193#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
194#define CONFIG_SYS_SDRAM0_MODT2 0x00000000
195#define CONFIG_SYS_SDRAM0_MODT3 0x00000000
196#define CONFIG_SYS_SDRAM0_CODT 0x00000020
197#define CONFIG_SYS_SDRAM0_RTR 0x06180000
198#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000
199#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
200#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
201#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
Dirk Eibach91d59902009-09-21 13:27:14 +0200202#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002
Dirk Eibach15cc3852011-10-04 11:13:55 +0200203#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000552
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200204#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
205#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000
206#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000
207#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000
208#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000
Dirk Eibach15cc3852011-10-04 11:13:55 +0200209#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000452
Dirk Eibach91d59902009-09-21 13:27:14 +0200210#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382
211#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200212#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
213#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
214#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
Dirk Eibach91d59902009-09-21 13:27:14 +0200215#define CONFIG_SYS_SDRAM0_RFDC 0x00000257
216#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200217#define CONFIG_SYS_SDRAM0_DLCR 0x00000000
218#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
Dirk Eibach15cc3852011-10-04 11:13:55 +0200219#define CONFIG_SYS_SDRAM0_WRDTR 0x86000823
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200220#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
221#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
Dirk Eibach91d59902009-09-21 13:27:14 +0200222#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15
Dirk Eibach15cc3852011-10-04 11:13:55 +0200223#define CONFIG_SYS_SDRAM0_MMODE 0x00000452
Dirk Eibach91d59902009-09-21 13:27:14 +0200224#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002
Dirk Eibachab4c62c2009-07-27 08:49:48 +0200225
226#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */
227
228/*
229 * I2C
230 */
231#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
232
233#define CONFIG_SYS_I2C_MULTI_EEPROMS
234#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
235#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
236#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
237#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
238
239/* I2C bootstrap EEPROM */
240#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
241#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
242#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
243
244/* I2C SYSMON */
245#define CONFIG_DTT_LM63 1 /* National LM63 */
246#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
247#define CONFIG_DTT_PWM_LOOKUPTABLE \
248 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
249#define CONFIG_DTT_TACH_LIMIT 0xa10
250
251/* RTC configuration */
252#define CONFIG_RTC_DS1337 1
253#define CONFIG_SYS_I2C_RTC_ADDR 0x68
254
255/*
256 * Ethernet
257 */
258#define CONFIG_IBM_EMAC4_V4 1
259
260#define CONFIG_HAS_ETH0
261#define CONFIG_HAS_ETH1
262
263#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
264#define CONFIG_PHY1_ADDR 3
265
266#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
267#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
268#define CONFIG_PHY_DYNAMIC_ANEG 1
269
270/*
271 * USB-OHCI
272 */
273#define CONFIG_USB_OHCI_NEW
274#define CONFIG_USB_STORAGE
275#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/
276#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
277#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
278#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
279#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
280#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
281
282/*
283 * Default environment variables
284 */
285#define CONFIG_EXTRA_ENV_SETTINGS \
286 CONFIG_AMCC_DEF_ENV \
287 CONFIG_AMCC_DEF_ENV_POWERPC \
288 CONFIG_AMCC_DEF_ENV_NOR_UPD \
289 "kernel_addr=fc000000\0" \
290 "fdt_addr=fc1e0000\0" \
291 "ramdisk_addr=fc200000\0" \
292 "pciconfighost=1\0" \
293 "pcie_mode=RP:RP\0" \
294 ""
295
296/*
297 * Commands additional to the ones defined in amcc-common.h
298 */
299#define CONFIG_CMD_CHIP_CONFIG
300#define CONFIG_CMD_DATE
301#define CONFIG_CMD_DTT
302#define CONFIG_CMD_EXT2
303#define CONFIG_CMD_FAT
304#define CONFIG_CMD_PCI
305#define CONFIG_CMD_SDRAM
306#define CONFIG_CMD_SNTP
307#define CONFIG_CMD_USB
308
309/* Partitions */
310#define CONFIG_MAC_PARTITION
311#define CONFIG_DOS_PARTITION
312#define CONFIG_ISO_PARTITION
313
314/*
315 * PCI stuff
316 */
317/* General PCI */
318#define CONFIG_PCI /* include pci support */
319#define CONFIG_PCI_PNP /* do pci plug-and-play */
320#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
321#define CONFIG_PCI_CONFIG_HOST_BRIDGE
322#define CONFIG_PCI_DISABLE_PCIE
323
324/* Board-specific PCI */
325#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
326#undef CONFIG_SYS_PCI_MASTER_INIT
327
328#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
329#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
330
331
332/*
333 * External Bus Controller (EBC) Setup
334 */
335
336/*
337 * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the
338 * boot EBC mapping only supports a maximum of 16MBytes
339 * (4.ff00.0000 - 4.ffff.ffff).
340 * To solve this problem, the FLASH has to get remapped to another
341 * EBC address which accepts bigger regions:
342 *
343 * 0xfc00.0000 -> 4.cc00.0000
344 */
345
346
347/* Memory Bank 0 (NOR-FLASH) initialization */
348#define CONFIG_SYS_EBC_PB0AP 0x10055e00
349#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
350
351/* Memory Bank 1 (NVRAM) initialization */
352#define CONFIG_SYS_EBC_PB1AP 0x02815480
353/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/
354#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000)
355
356/* Memory Bank 2 (UART) initialization */
357#define CONFIG_SYS_EBC_PB2AP 0x02815480
358/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/
359#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000)
360
361/* Memory Bank 3 (IO) initialization */
362#define CONFIG_SYS_EBC_PB3AP 0x02815480
363/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/
364#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000)
365
366/*
367 * PPC4xx GPIO Configuration
368 */
369/* 460EX: Use USB configuration */
370#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
371{ \
372/* GPIO Core 0 */ \
373{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
374{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
375{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
376{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
377{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
378{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
379{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
380{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
381{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
382{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
383{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
384{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
385{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
386{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
387{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
388{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
389{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
390{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
391{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
392{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
393{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
394{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
395{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
396{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
397{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
398{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
399{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
400{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
401{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
402{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
403{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
404{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
405}, \
406{ \
407/* GPIO Core 1 */ \
408{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
409{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
410{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
411{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
412{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
413{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
414{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
415{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
416{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
417{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
418{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
419{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
420{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
421{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
422{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
423{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
424{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
425{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
426{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \
427{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \
428{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \
429{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \
430{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \
431{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \
432{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \
433{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
434{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
435{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
436{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
437{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \
438{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \
439{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \
440} \
441}
442
443#endif /* __CONFIG_H */