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Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05301/*
2 * (C) Copyright 2015 Xilinx, Inc,
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0
6 */
7
8#ifndef _ZYNQMPPL_H_
9#define _ZYNQMPPL_H_
10
11#include <xilinx.h>
12
Michal Simek47e60cb2016-02-01 15:05:58 +010013#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053014#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
15#define ZYNQMP_FPGA_OP_INIT (1 << 0)
16#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
17#define ZYNQMP_FPGA_OP_DONE (1 << 2)
18
Soren Brinkmann0cba6ab2016-09-29 11:44:41 -070019#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
20#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
21 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
22#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
23#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
24
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053025extern struct xilinx_fpga_op zynqmp_op;
26
27#define XILINX_ZYNQMP_DESC \
28{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
29
30#endif /* _ZYNQMPPL_H_ */