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Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +02001#ifndef __ASM_ARM_SYSTEM_H
2#define __ASM_ARM_SYSTEM_H
3
David Feng0ae76532013-12-14 11:47:35 +08004#ifdef CONFIG_ARM64
5
6/*
7 * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
8 */
9#define CR_M (1 << 0) /* MMU enable */
10#define CR_A (1 << 1) /* Alignment abort enable */
11#define CR_C (1 << 2) /* Dcache enable */
12#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
13#define CR_I (1 << 12) /* Icache enable */
14#define CR_WXN (1 << 19) /* Write Permision Imply XN */
15#define CR_EE (1 << 25) /* Exception (Big) Endian */
16
17#define PGTABLE_SIZE (0x10000)
18
19#ifndef __ASSEMBLY__
20
21#define isb() \
22 ({asm volatile( \
23 "isb" : : : "memory"); \
24 })
25
26#define wfi() \
27 ({asm volatile( \
28 "wfi" : : : "memory"); \
29 })
30
31static inline unsigned int current_el(void)
32{
33 unsigned int el;
34 asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
35 return el >> 2;
36}
37
38static inline unsigned int get_sctlr(void)
39{
40 unsigned int el, val;
41
42 el = current_el();
43 if (el == 1)
44 asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
45 else if (el == 2)
46 asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
47 else
48 asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
49
50 return val;
51}
52
53static inline void set_sctlr(unsigned int val)
54{
55 unsigned int el;
56
57 el = current_el();
58 if (el == 1)
59 asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
60 else if (el == 2)
61 asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
62 else
63 asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
64
65 asm volatile("isb");
66}
67
68void __asm_flush_dcache_all(void);
York Sun1e6ad552014-02-26 13:26:04 -080069void __asm_invalidate_dcache_all(void);
David Feng0ae76532013-12-14 11:47:35 +080070void __asm_flush_dcache_range(u64 start, u64 end);
71void __asm_invalidate_tlb_all(void);
72void __asm_invalidate_icache_all(void);
73
74void armv8_switch_to_el2(void);
75void armv8_switch_to_el1(void);
76void gic_init(void);
77void gic_send_sgi(unsigned long sgino);
78void wait_for_wakeup(void);
79void smp_kick_all_cpus(void);
80
York Sun2f78eae2014-06-23 15:15:54 -070081void flush_l3_cache(void);
82
David Feng0ae76532013-12-14 11:47:35 +080083#endif /* __ASSEMBLY__ */
84
85#else /* CONFIG_ARM64 */
86
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +020087#ifdef __KERNEL__
88
89#define CPU_ARCH_UNKNOWN 0
90#define CPU_ARCH_ARMv3 1
91#define CPU_ARCH_ARMv4 2
92#define CPU_ARCH_ARMv4T 3
93#define CPU_ARCH_ARMv5 4
94#define CPU_ARCH_ARMv5T 5
95#define CPU_ARCH_ARMv5TE 6
96#define CPU_ARCH_ARMv5TEJ 7
97#define CPU_ARCH_ARMv6 8
98#define CPU_ARCH_ARMv7 9
99
100/*
101 * CR1 bits (CP#15 CR1)
102 */
103#define CR_M (1 << 0) /* MMU enable */
104#define CR_A (1 << 1) /* Alignment abort enable */
105#define CR_C (1 << 2) /* Dcache enable */
106#define CR_W (1 << 3) /* Write buffer enable */
107#define CR_P (1 << 4) /* 32-bit exception handler */
108#define CR_D (1 << 5) /* 32-bit data address range */
109#define CR_L (1 << 6) /* Implementation defined */
110#define CR_B (1 << 7) /* Big endian */
111#define CR_S (1 << 8) /* System MMU protection */
112#define CR_R (1 << 9) /* ROM MMU protection */
113#define CR_F (1 << 10) /* Implementation defined */
114#define CR_Z (1 << 11) /* Implementation defined */
115#define CR_I (1 << 12) /* Icache enable */
116#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
117#define CR_RR (1 << 14) /* Round Robin cache replacement */
118#define CR_L4 (1 << 15) /* LDR pc can set T bit */
119#define CR_DT (1 << 16)
120#define CR_IT (1 << 18)
121#define CR_ST (1 << 19)
122#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
123#define CR_U (1 << 22) /* Unaligned access operation */
124#define CR_XP (1 << 23) /* Extended page tables */
125#define CR_VE (1 << 24) /* Vectored interrupts */
126#define CR_EE (1 << 25) /* Exception (Big) Endian */
127#define CR_TRE (1 << 28) /* TEX remap enable */
128#define CR_AFE (1 << 29) /* Access flag enable */
129#define CR_TE (1 << 30) /* Thumb exception enable */
130
David Feng0ae76532013-12-14 11:47:35 +0800131#define PGTABLE_SIZE (4096 * 4)
132
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200133/*
134 * This is used to ensure the compiler did actually allocate the register we
135 * asked it for some inline assembly sequences. Apparently we can't trust
136 * the compiler from one version to another so a bit of paranoia won't hurt.
137 * This string is meant to be concatenated with the inline asm string and
138 * will cause compilation to stop on mismatch.
139 * (for details, see gcc PR 15089)
140 */
141#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
142
143#ifndef __ASSEMBLY__
144
145#define isb() __asm__ __volatile__ ("" : : : "memory")
146
147#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
148
Rob Herring2ff467c2012-12-02 17:06:21 +0000149#ifdef __ARM_ARCH_7A__
150#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
151#else
152#define wfi()
153#endif
154
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200155static inline unsigned int get_cr(void)
156{
157 unsigned int val;
158 asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
159 return val;
160}
161
162static inline void set_cr(unsigned int val)
163{
164 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
165 : : "r" (val) : "cc");
166 isb();
167}
168
R Sricharande63ac22013-03-04 20:04:45 +0000169static inline unsigned int get_dacr(void)
170{
171 unsigned int val;
172 asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
173 return val;
174}
175
176static inline void set_dacr(unsigned int val)
177{
178 asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
179 : : "r" (val) : "cc");
180 isb();
181}
182
Simon Glass0dde7f52012-10-17 13:24:53 +0000183/* options available for data cache on each page */
184enum dcache_option {
185 DCACHE_OFF = 0x12,
186 DCACHE_WRITETHROUGH = 0x1a,
187 DCACHE_WRITEBACK = 0x1e,
Marek Vasutff7e9702014-09-15 02:44:36 +0200188 DCACHE_WRITEALLOC = 0x16,
Simon Glass0dde7f52012-10-17 13:24:53 +0000189};
190
191/* Size of an MMU section */
192enum {
193 MMU_SECTION_SHIFT = 20,
194 MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
195};
196
197/**
198 * Change the cache settings for a region.
199 *
200 * \param start start address of memory region to change
201 * \param size size of memory region to change
202 * \param option dcache option to select
203 */
Thierry Reding25026fa2014-08-26 17:34:21 +0200204void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
Simon Glass0dde7f52012-10-17 13:24:53 +0000205 enum dcache_option option);
206
207/**
208 * Register an update to the page tables, and flush the TLB
209 *
210 * \param start start address of update in page table
211 * \param stop stop address of update in page table
212 */
213void mmu_page_table_flush(unsigned long start, unsigned long stop);
214
Thierry Reding1dfdd9b2014-12-09 22:25:22 -0700215#ifdef CONFIG_SYS_NONCACHED_MEMORY
216void noncached_init(void);
217phys_addr_t noncached_alloc(size_t size, size_t align);
218#endif /* CONFIG_SYS_NONCACHED_MEMORY */
219
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200220#endif /* __ASSEMBLY__ */
221
222#define arch_align_stack(x) (x)
223
224#endif /* __KERNEL__ */
225
David Feng0ae76532013-12-14 11:47:35 +0800226#endif /* CONFIG_ARM64 */
227
Jean-Christophe PLAGNIOL-VILLARD677e62f2009-04-05 13:02:43 +0200228#endif