Andrew Davis | ad84129 | 2023-04-11 13:24:55 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 2 | /* |
Andrew Davis | ad84129 | 2023-04-11 13:24:55 -0500 | [diff] [blame] | 3 | * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* AM437x SK EVM */ |
| 7 | |
| 8 | /dts-v1/; |
| 9 | |
| 10 | #include "am4372.dtsi" |
| 11 | #include <dt-bindings/pinctrl/am43xx.h> |
| 12 | #include <dt-bindings/pwm/pwm.h> |
| 13 | #include <dt-bindings/gpio/gpio.h> |
| 14 | #include <dt-bindings/input/input.h> |
| 15 | |
| 16 | / { |
| 17 | model = "TI AM437x SK EVM"; |
| 18 | compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43"; |
| 19 | |
| 20 | aliases { |
| 21 | display0 = &lcd0; |
| 22 | }; |
| 23 | |
| 24 | chosen { |
| 25 | stdout-path = &uart0; |
Mugunthan V N | 34afc61 | 2015-12-24 16:08:09 +0530 | [diff] [blame] | 26 | tick-timer = &timer2; |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 27 | }; |
| 28 | |
| 29 | backlight { |
| 30 | compatible = "pwm-backlight"; |
| 31 | pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; |
| 32 | brightness-levels = <0 51 53 56 62 75 101 152 255>; |
| 33 | default-brightness-level = <8>; |
| 34 | }; |
| 35 | |
| 36 | sound { |
| 37 | compatible = "ti,da830-evm-audio"; |
| 38 | ti,model = "AM437x-SK-EVM"; |
| 39 | ti,audio-codec = <&tlv320aic3106>; |
| 40 | ti,mcasp-controller = <&mcasp1>; |
| 41 | ti,codec-clock-rate = <24000000>; |
| 42 | ti,audio-routing = |
| 43 | "Headphone Jack", "HPLOUT", |
| 44 | "Headphone Jack", "HPROUT"; |
| 45 | }; |
| 46 | |
| 47 | matrix_keypad: matrix_keypad@0 { |
| 48 | compatible = "gpio-matrix-keypad"; |
| 49 | |
| 50 | pinctrl-names = "default"; |
| 51 | pinctrl-0 = <&matrix_keypad_pins>; |
| 52 | |
| 53 | debounce-delay-ms = <5>; |
| 54 | col-scan-delay-us = <5>; |
| 55 | |
| 56 | row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */ |
| 57 | &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */ |
| 58 | |
| 59 | col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */ |
| 60 | &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */ |
| 61 | |
| 62 | linux,keymap = < |
| 63 | MATRIX_KEY(0, 0, KEY_DOWN) |
| 64 | MATRIX_KEY(0, 1, KEY_RIGHT) |
| 65 | MATRIX_KEY(1, 0, KEY_LEFT) |
| 66 | MATRIX_KEY(1, 1, KEY_UP) |
| 67 | >; |
| 68 | }; |
| 69 | |
| 70 | leds { |
| 71 | compatible = "gpio-leds"; |
| 72 | |
| 73 | pinctrl-names = "default"; |
| 74 | pinctrl-0 = <&leds_pins>; |
| 75 | |
| 76 | led@0 { |
| 77 | label = "am437x-sk:red:heartbeat"; |
| 78 | gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ |
| 79 | linux,default-trigger = "heartbeat"; |
| 80 | default-state = "off"; |
| 81 | }; |
| 82 | |
| 83 | led@1 { |
| 84 | label = "am437x-sk:green:mmc1"; |
| 85 | gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ |
| 86 | linux,default-trigger = "mmc0"; |
| 87 | default-state = "off"; |
| 88 | }; |
| 89 | |
| 90 | led@2 { |
| 91 | label = "am437x-sk:blue:cpu0"; |
| 92 | gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ |
| 93 | linux,default-trigger = "cpu0"; |
| 94 | default-state = "off"; |
| 95 | }; |
| 96 | |
| 97 | led@3 { |
| 98 | label = "am437x-sk:blue:usr3"; |
| 99 | gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ |
| 100 | default-state = "off"; |
| 101 | }; |
| 102 | }; |
| 103 | |
| 104 | lcd0: display { |
| 105 | compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; |
| 106 | label = "lcd"; |
| 107 | |
| 108 | pinctrl-names = "default"; |
| 109 | pinctrl-0 = <&lcd_pins>; |
| 110 | |
| 111 | enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; |
| 112 | |
| 113 | panel-timing { |
| 114 | clock-frequency = <9000000>; |
| 115 | hactive = <480>; |
| 116 | vactive = <272>; |
| 117 | hfront-porch = <2>; |
| 118 | hback-porch = <2>; |
| 119 | hsync-len = <41>; |
| 120 | vfront-porch = <2>; |
| 121 | vback-porch = <2>; |
| 122 | vsync-len = <10>; |
| 123 | hsync-active = <0>; |
| 124 | vsync-active = <0>; |
| 125 | de-active = <1>; |
| 126 | pixelclk-active = <1>; |
| 127 | }; |
| 128 | |
| 129 | port { |
| 130 | lcd_in: endpoint { |
| 131 | remote-endpoint = <&dpi_out>; |
| 132 | }; |
| 133 | }; |
| 134 | }; |
| 135 | }; |
| 136 | |
| 137 | &am43xx_pinmux { |
| 138 | matrix_keypad_pins: matrix_keypad_pins { |
| 139 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 140 | AM4372_IOPAD(0xa4c, PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */ |
| 141 | AM4372_IOPAD(0xa50, PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */ |
| 142 | AM4372_IOPAD(0xa54, PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */ |
| 143 | AM4372_IOPAD(0xa58, PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 144 | >; |
| 145 | }; |
| 146 | |
| 147 | leds_pins: leds_pins { |
| 148 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 149 | AM4372_IOPAD(0xa28, PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */ |
| 150 | AM4372_IOPAD(0xa2c, PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */ |
| 151 | AM4372_IOPAD(0xa30, PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */ |
| 152 | AM4372_IOPAD(0xa34, PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 153 | >; |
| 154 | }; |
| 155 | |
| 156 | i2c0_pins: i2c0_pins { |
| 157 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 158 | AM4372_IOPAD(0x988, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ |
| 159 | AM4372_IOPAD(0x98c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 160 | >; |
| 161 | }; |
| 162 | |
| 163 | i2c1_pins: i2c1_pins { |
| 164 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 165 | AM4372_IOPAD(0x95c, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ |
| 166 | AM4372_IOPAD(0x958, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 167 | >; |
| 168 | }; |
| 169 | |
| 170 | mmc1_pins: pinmux_mmc1_pins { |
| 171 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 172 | AM4372_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */ |
| 173 | AM4372_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */ |
| 174 | AM4372_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */ |
| 175 | AM4372_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */ |
| 176 | AM4372_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ |
| 177 | AM4372_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ |
| 178 | AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 179 | >; |
| 180 | }; |
| 181 | |
| 182 | ecap0_pins: backlight_pins { |
| 183 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 184 | AM4372_IOPAD(0x964, PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 185 | >; |
| 186 | }; |
| 187 | |
| 188 | edt_ft5306_ts_pins: edt_ft5306_ts_pins { |
| 189 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 190 | AM4372_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */ |
| 191 | AM4372_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 192 | >; |
| 193 | }; |
| 194 | |
| 195 | vpfe0_pins_default: vpfe0_pins_default { |
| 196 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 197 | AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ |
| 198 | AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ |
| 199 | AM4372_IOPAD(0x9b8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/ |
| 200 | AM4372_IOPAD(0x9bc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/ |
| 201 | AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ |
| 202 | AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ |
| 203 | AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ |
| 204 | AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ |
| 205 | AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ |
| 206 | AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ |
| 207 | AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ |
| 208 | AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ |
| 209 | AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ |
| 210 | AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ |
| 211 | AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 212 | >; |
| 213 | }; |
| 214 | |
| 215 | vpfe0_pins_sleep: vpfe0_pins_sleep { |
| 216 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 217 | AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 218 | AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 219 | AM4372_IOPAD(0x9b8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 220 | AM4372_IOPAD(0x9bc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 221 | AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 222 | AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 223 | AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 224 | AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 225 | AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 226 | AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 227 | AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 228 | AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 229 | AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 230 | AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
| 231 | AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 232 | >; |
| 233 | }; |
| 234 | |
| 235 | cpsw_default: cpsw_default { |
| 236 | pinctrl-single,pins = < |
| 237 | /* Slave 1 */ |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 238 | AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ |
| 239 | AM4372_IOPAD(0x914, PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ |
| 240 | AM4372_IOPAD(0x928, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ |
| 241 | AM4372_IOPAD(0x924, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ |
| 242 | AM4372_IOPAD(0x920, PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */ |
| 243 | AM4372_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */ |
| 244 | AM4372_IOPAD(0x930, PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ |
| 245 | AM4372_IOPAD(0x918, PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ |
| 246 | AM4372_IOPAD(0x940, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ |
| 247 | AM4372_IOPAD(0x93c, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ |
| 248 | AM4372_IOPAD(0x938, PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */ |
| 249 | AM4372_IOPAD(0x934, PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 250 | |
| 251 | /* Slave 2 */ |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 252 | AM4372_IOPAD(0x858, PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ |
| 253 | AM4372_IOPAD(0x840, PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ |
| 254 | AM4372_IOPAD(0x854, PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ |
| 255 | AM4372_IOPAD(0x850, PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ |
| 256 | AM4372_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ |
| 257 | AM4372_IOPAD(0x848, PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ |
| 258 | AM4372_IOPAD(0x85c, PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ |
| 259 | AM4372_IOPAD(0x844, PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */ |
| 260 | AM4372_IOPAD(0x86c, PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ |
| 261 | AM4372_IOPAD(0x868, PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ |
| 262 | AM4372_IOPAD(0x864, PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ |
| 263 | AM4372_IOPAD(0x860, PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 264 | >; |
| 265 | }; |
| 266 | |
| 267 | cpsw_sleep: cpsw_sleep { |
| 268 | pinctrl-single,pins = < |
| 269 | /* Slave 1 reset value */ |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 270 | AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 271 | AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 272 | AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 273 | AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 274 | AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 275 | AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 276 | AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 277 | AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 278 | AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 279 | AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 280 | AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 281 | AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 282 | |
| 283 | /* Slave 2 reset value */ |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 284 | AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 285 | AM4372_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 286 | AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 287 | AM4372_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 288 | AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 289 | AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 290 | AM4372_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 291 | AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 292 | AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 293 | AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 294 | AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 295 | AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 296 | >; |
| 297 | }; |
| 298 | |
| 299 | davinci_mdio_default: davinci_mdio_default { |
| 300 | pinctrl-single,pins = < |
| 301 | /* MDIO */ |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 302 | AM4372_IOPAD(0x948, PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ |
| 303 | AM4372_IOPAD(0x94c, PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 304 | >; |
| 305 | }; |
| 306 | |
| 307 | davinci_mdio_sleep: davinci_mdio_sleep { |
| 308 | pinctrl-single,pins = < |
| 309 | /* MDIO reset value */ |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 310 | AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) |
| 311 | AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 312 | >; |
| 313 | }; |
| 314 | |
| 315 | dss_pins: dss_pins { |
| 316 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 317 | AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */ |
| 318 | AM4372_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) |
| 319 | AM4372_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) |
| 320 | AM4372_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) |
| 321 | AM4372_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) |
| 322 | AM4372_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) |
| 323 | AM4372_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) |
| 324 | AM4372_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */ |
| 325 | AM4372_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */ |
| 326 | AM4372_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) |
| 327 | AM4372_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) |
| 328 | AM4372_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) |
| 329 | AM4372_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) |
| 330 | AM4372_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) |
| 331 | AM4372_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) |
| 332 | AM4372_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) |
| 333 | AM4372_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) |
| 334 | AM4372_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) |
| 335 | AM4372_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) |
| 336 | AM4372_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) |
| 337 | AM4372_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) |
| 338 | AM4372_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) |
| 339 | AM4372_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) |
| 340 | AM4372_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */ |
| 341 | AM4372_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */ |
| 342 | AM4372_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */ |
| 343 | AM4372_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */ |
| 344 | AM4372_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 345 | |
| 346 | >; |
| 347 | }; |
| 348 | |
| 349 | qspi_pins: qspi_pins { |
| 350 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 351 | AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */ |
| 352 | AM4372_IOPAD(0x888, PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */ |
| 353 | AM4372_IOPAD(0x890, PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */ |
| 354 | AM4372_IOPAD(0x894, PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */ |
| 355 | AM4372_IOPAD(0x898, PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */ |
| 356 | AM4372_IOPAD(0x89c, PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 357 | >; |
| 358 | }; |
| 359 | |
| 360 | mcasp1_pins: mcasp1_pins { |
| 361 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 362 | AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ |
| 363 | AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ |
| 364 | AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ |
| 365 | AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 366 | >; |
| 367 | }; |
| 368 | |
| 369 | lcd_pins: lcd_pins { |
| 370 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 371 | AM4372_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 372 | >; |
| 373 | }; |
| 374 | |
| 375 | usb1_pins: usb1_pins { |
| 376 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 377 | AM4372_IOPAD(0xac0, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 378 | >; |
| 379 | }; |
| 380 | |
| 381 | usb2_pins: usb2_pins { |
| 382 | pinctrl-single,pins = < |
Andrew Davis | 1dfb028 | 2023-04-11 13:25:04 -0500 | [diff] [blame] | 383 | AM4372_IOPAD(0xac4, PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */ |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 384 | >; |
| 385 | }; |
| 386 | }; |
| 387 | |
| 388 | &i2c0 { |
| 389 | status = "okay"; |
| 390 | pinctrl-names = "default"; |
| 391 | pinctrl-0 = <&i2c0_pins>; |
| 392 | clock-frequency = <400000>; |
| 393 | |
| 394 | tps@24 { |
| 395 | compatible = "ti,tps65218"; |
| 396 | reg = <0x24>; |
| 397 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| 398 | interrupt-controller; |
| 399 | #interrupt-cells = <2>; |
| 400 | |
| 401 | dcdc1: regulator-dcdc1 { |
| 402 | compatible = "ti,tps65218-dcdc1"; |
| 403 | /* VDD_CORE limits min of OPP50 and max of OPP100 */ |
| 404 | regulator-name = "vdd_core"; |
| 405 | regulator-min-microvolt = <912000>; |
| 406 | regulator-max-microvolt = <1144000>; |
| 407 | regulator-boot-on; |
| 408 | regulator-always-on; |
| 409 | }; |
| 410 | |
| 411 | dcdc2: regulator-dcdc2 { |
| 412 | compatible = "ti,tps65218-dcdc2"; |
| 413 | /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ |
| 414 | regulator-name = "vdd_mpu"; |
| 415 | regulator-min-microvolt = <912000>; |
| 416 | regulator-max-microvolt = <1378000>; |
| 417 | regulator-boot-on; |
| 418 | regulator-always-on; |
| 419 | }; |
| 420 | |
| 421 | dcdc3: regulator-dcdc3 { |
| 422 | compatible = "ti,tps65218-dcdc3"; |
| 423 | regulator-name = "vdds_ddr"; |
| 424 | regulator-min-microvolt = <1500000>; |
| 425 | regulator-max-microvolt = <1500000>; |
| 426 | regulator-boot-on; |
| 427 | regulator-always-on; |
| 428 | }; |
| 429 | |
| 430 | dcdc4: regulator-dcdc4 { |
| 431 | compatible = "ti,tps65218-dcdc4"; |
| 432 | regulator-name = "v3_3d"; |
| 433 | regulator-min-microvolt = <3300000>; |
| 434 | regulator-max-microvolt = <3300000>; |
| 435 | regulator-boot-on; |
| 436 | regulator-always-on; |
| 437 | }; |
| 438 | |
| 439 | ldo1: regulator-ldo1 { |
| 440 | compatible = "ti,tps65218-ldo1"; |
| 441 | regulator-name = "v1_8d"; |
| 442 | regulator-min-microvolt = <1800000>; |
| 443 | regulator-max-microvolt = <1800000>; |
| 444 | regulator-boot-on; |
| 445 | regulator-always-on; |
| 446 | }; |
| 447 | |
| 448 | power-button { |
| 449 | compatible = "ti,tps65218-pwrbutton"; |
| 450 | status = "okay"; |
| 451 | interrupts = <3 IRQ_TYPE_EDGE_BOTH>; |
| 452 | }; |
| 453 | }; |
| 454 | |
| 455 | at24@50 { |
| 456 | compatible = "at24,24c256"; |
| 457 | pagesize = <64>; |
| 458 | reg = <0x50>; |
| 459 | }; |
| 460 | }; |
| 461 | |
| 462 | &i2c1 { |
| 463 | status = "okay"; |
| 464 | pinctrl-names = "default"; |
| 465 | pinctrl-0 = <&i2c1_pins>; |
| 466 | clock-frequency = <400000>; |
| 467 | |
| 468 | edt-ft5306@38 { |
| 469 | status = "okay"; |
| 470 | compatible = "edt,edt-ft5306", "edt,edt-ft5x06"; |
| 471 | pinctrl-names = "default"; |
| 472 | pinctrl-0 = <&edt_ft5306_ts_pins>; |
| 473 | |
| 474 | reg = <0x38>; |
| 475 | interrupt-parent = <&gpio0>; |
| 476 | interrupts = <31 0>; |
| 477 | |
| 478 | reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; |
| 479 | |
| 480 | touchscreen-size-x = <480>; |
| 481 | touchscreen-size-y = <272>; |
| 482 | }; |
| 483 | |
| 484 | tlv320aic3106: tlv320aic3106@1b { |
| 485 | compatible = "ti,tlv320aic3106"; |
| 486 | reg = <0x1b>; |
| 487 | status = "okay"; |
| 488 | |
| 489 | /* Regulators */ |
| 490 | AVDD-supply = <&dcdc4>; |
| 491 | IOVDD-supply = <&dcdc4>; |
| 492 | DRVDD-supply = <&dcdc4>; |
| 493 | DVDD-supply = <&ldo1>; |
| 494 | }; |
| 495 | |
| 496 | lis331dlh@18 { |
| 497 | compatible = "st,lis331dlh"; |
| 498 | reg = <0x18>; |
| 499 | status = "okay"; |
| 500 | |
| 501 | Vdd-supply = <&dcdc4>; |
| 502 | Vdd_IO-supply = <&dcdc4>; |
| 503 | interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>; |
| 504 | }; |
| 505 | }; |
| 506 | |
| 507 | &epwmss0 { |
| 508 | status = "okay"; |
| 509 | }; |
| 510 | |
| 511 | &ecap0 { |
| 512 | status = "okay"; |
| 513 | pinctrl-names = "default"; |
| 514 | pinctrl-0 = <&ecap0_pins>; |
| 515 | }; |
| 516 | |
| 517 | &gpio0 { |
| 518 | status = "okay"; |
| 519 | }; |
| 520 | |
| 521 | &gpio1 { |
| 522 | status = "okay"; |
| 523 | }; |
| 524 | |
| 525 | &gpio5 { |
| 526 | status = "okay"; |
| 527 | }; |
| 528 | |
| 529 | &mmc1 { |
| 530 | status = "okay"; |
| 531 | pinctrl-names = "default"; |
| 532 | pinctrl-0 = <&mmc1_pins>; |
| 533 | |
| 534 | vmmc-supply = <&dcdc4>; |
| 535 | bus-width = <4>; |
Mugunthan V N | 103afa2 | 2016-04-04 17:28:02 +0530 | [diff] [blame] | 536 | cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 537 | }; |
| 538 | |
| 539 | &usb2_phy1 { |
| 540 | status = "okay"; |
| 541 | }; |
| 542 | |
| 543 | &usb1 { |
| 544 | dr_mode = "peripheral"; |
| 545 | status = "okay"; |
| 546 | pinctrl-names = "default"; |
| 547 | pinctrl-0 = <&usb1_pins>; |
| 548 | }; |
| 549 | |
| 550 | &usb2_phy2 { |
| 551 | status = "okay"; |
| 552 | }; |
| 553 | |
| 554 | &usb2 { |
| 555 | dr_mode = "host"; |
| 556 | status = "okay"; |
| 557 | pinctrl-names = "default"; |
| 558 | pinctrl-0 = <&usb2_pins>; |
| 559 | }; |
| 560 | |
| 561 | &qspi { |
| 562 | status = "okay"; |
| 563 | pinctrl-names = "default"; |
| 564 | pinctrl-0 = <&qspi_pins>; |
| 565 | |
| 566 | spi-max-frequency = <48000000>; |
| 567 | m25p80@0 { |
Neil Armstrong | ffd4c7c | 2019-02-10 10:16:20 +0000 | [diff] [blame] | 568 | compatible = "mx66l51235l","jedec,spi-nor"; |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 569 | spi-max-frequency = <48000000>; |
| 570 | reg = <0>; |
| 571 | spi-cpol; |
| 572 | spi-cpha; |
| 573 | spi-tx-bus-width = <1>; |
| 574 | spi-rx-bus-width = <4>; |
| 575 | #address-cells = <1>; |
| 576 | #size-cells = <1>; |
| 577 | |
| 578 | /* MTD partition table. |
| 579 | * The ROM checks the first 512KiB |
| 580 | * for a valid file to boot(XIP). |
| 581 | */ |
| 582 | partition@0 { |
| 583 | label = "QSPI.U_BOOT"; |
| 584 | reg = <0x00000000 0x000080000>; |
| 585 | }; |
| 586 | partition@1 { |
| 587 | label = "QSPI.U_BOOT.backup"; |
| 588 | reg = <0x00080000 0x00080000>; |
| 589 | }; |
| 590 | partition@2 { |
| 591 | label = "QSPI.U-BOOT-SPL_OS"; |
| 592 | reg = <0x00100000 0x00010000>; |
| 593 | }; |
| 594 | partition@3 { |
| 595 | label = "QSPI.U_BOOT_ENV"; |
| 596 | reg = <0x00110000 0x00010000>; |
| 597 | }; |
| 598 | partition@4 { |
| 599 | label = "QSPI.U-BOOT-ENV.backup"; |
| 600 | reg = <0x00120000 0x00010000>; |
| 601 | }; |
| 602 | partition@5 { |
| 603 | label = "QSPI.KERNEL"; |
| 604 | reg = <0x00130000 0x0800000>; |
| 605 | }; |
| 606 | partition@6 { |
| 607 | label = "QSPI.FILESYSTEM"; |
| 608 | reg = <0x00930000 0x36D0000>; |
| 609 | }; |
| 610 | }; |
| 611 | }; |
| 612 | |
| 613 | &mac { |
| 614 | pinctrl-names = "default", "sleep"; |
| 615 | pinctrl-0 = <&cpsw_default>; |
| 616 | pinctrl-1 = <&cpsw_sleep>; |
| 617 | dual_emac = <1>; |
| 618 | status = "okay"; |
| 619 | }; |
| 620 | |
| 621 | &davinci_mdio { |
| 622 | pinctrl-names = "default", "sleep"; |
| 623 | pinctrl-0 = <&davinci_mdio_default>; |
| 624 | pinctrl-1 = <&davinci_mdio_sleep>; |
| 625 | status = "okay"; |
Grygorii Strashko | b1fe4fe | 2019-08-31 10:30:33 +0300 | [diff] [blame] | 626 | |
| 627 | ethphy0: ethernet-phy@4 { |
| 628 | reg = <4>; |
| 629 | }; |
| 630 | |
| 631 | ethphy1: ethernet-phy@5 { |
| 632 | reg = <5>; |
| 633 | }; |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 634 | }; |
| 635 | |
| 636 | &cpsw_emac0 { |
Grygorii Strashko | b1fe4fe | 2019-08-31 10:30:33 +0300 | [diff] [blame] | 637 | phy-handle = <ðphy0>; |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 638 | phy-mode = "rgmii"; |
| 639 | dual_emac_res_vlan = <1>; |
| 640 | }; |
| 641 | |
| 642 | &cpsw_emac1 { |
Grygorii Strashko | b1fe4fe | 2019-08-31 10:30:33 +0300 | [diff] [blame] | 643 | phy-handle = <ðphy1>; |
Mugunthan V N | 7a837bc | 2015-09-28 16:17:52 +0530 | [diff] [blame] | 644 | phy-mode = "rgmii"; |
| 645 | dual_emac_res_vlan = <2>; |
| 646 | }; |
| 647 | |
| 648 | &elm { |
| 649 | status = "okay"; |
| 650 | }; |
| 651 | |
| 652 | &mcasp1 { |
| 653 | pinctrl-names = "default"; |
| 654 | pinctrl-0 = <&mcasp1_pins>; |
| 655 | |
| 656 | status = "okay"; |
| 657 | |
| 658 | op-mode = <0>; |
| 659 | tdm-slots = <2>; |
| 660 | serial-dir = < |
| 661 | 0 0 1 2 |
| 662 | >; |
| 663 | |
| 664 | tx-num-evt = <1>; |
| 665 | rx-num-evt = <1>; |
| 666 | }; |
| 667 | |
| 668 | &dss { |
| 669 | status = "okay"; |
| 670 | |
| 671 | pinctrl-names = "default"; |
| 672 | pinctrl-0 = <&dss_pins>; |
| 673 | |
| 674 | port { |
| 675 | dpi_out: endpoint@0 { |
| 676 | remote-endpoint = <&lcd_in>; |
| 677 | data-lines = <24>; |
| 678 | }; |
| 679 | }; |
| 680 | }; |
| 681 | |
| 682 | &rtc { |
| 683 | status = "okay"; |
| 684 | }; |
| 685 | |
| 686 | &wdt { |
| 687 | status = "okay"; |
| 688 | }; |
| 689 | |
| 690 | &cpu { |
| 691 | cpu0-supply = <&dcdc2>; |
| 692 | }; |
| 693 | |
| 694 | &vpfe0 { |
| 695 | status = "okay"; |
| 696 | pinctrl-names = "default", "sleep"; |
| 697 | pinctrl-0 = <&vpfe0_pins_default>; |
| 698 | pinctrl-1 = <&vpfe0_pins_sleep>; |
| 699 | |
| 700 | /* Camera port */ |
| 701 | port { |
| 702 | vpfe0_ep: endpoint { |
| 703 | /* remote-endpoint = <&sensor>; add once we have it */ |
| 704 | ti,am437x-vpfe-interface = <0>; |
| 705 | bus-width = <8>; |
| 706 | hsync-active = <0>; |
| 707 | vsync-active = <0>; |
| 708 | }; |
| 709 | }; |
| 710 | }; |