blob: 7d708084042d729d5d5b2f30553c7401d6573b53 [file] [log] [blame]
Weijie Gaoe053ccf2022-09-09 19:59:16 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7981.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "mt7981-rfb";
15 compatible = "mediatek,mt7981", "mediatek,mt7981-sd-rfb";
16 chosen {
17 stdout-path = &uart0;
18 tick-timer = &timer0;
19 };
20
Weijie Gao5fd6d4c2023-07-19 17:15:41 +080021 memory@40000000 {
22 device_type = "memory";
23 reg = <0x40000000 0x10000000>;
24 };
25
Weijie Gaoe053ccf2022-09-09 19:59:16 +080026 reg_3p3v: regulator-3p3v {
27 compatible = "regulator-fixed";
28 regulator-name = "fixed-3.3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-boot-on;
32 regulator-always-on;
33 };
34};
35
36&uart0 {
37 status = "okay";
38};
39
40&uart1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&uart1_pins>;
43 status = "disabled";
44};
45
46&eth {
47 status = "okay";
48 mediatek,gmac-id = <0>;
Weijie Gaoaef54ea2023-07-19 17:17:18 +080049 phy-mode = "2500base-x";
Weijie Gaoe053ccf2022-09-09 19:59:16 +080050 mediatek,switch = "mt7531";
51 reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
52
53 fixed-link {
Weijie Gaoaef54ea2023-07-19 17:17:18 +080054 speed = <2500>;
Weijie Gaoe053ccf2022-09-09 19:59:16 +080055 full-duplex;
56 };
57};
58
59&pinctrl {
60 spic_pins: spi1-pins-func-1 {
61 mux {
62 function = "spi";
63 groups = "spi1_1";
64 };
65 };
66
67 uart1_pins: spi1-pins-func-3 {
68 mux {
69 function = "uart";
70 groups = "uart1_2";
71 };
72 };
73
74 /* pin15 as pwm0 */
75 one_pwm_pins: one-pwm-pins {
76 mux {
77 function = "pwm";
78 groups = "pwm0_1";
79 };
80 };
81
82 /* pin15 as pwm0 and pin14 as pwm1 */
83 two_pwm_pins: two-pwm-pins {
84 mux {
85 function = "pwm";
86 groups = "pwm0_1", "pwm1_0";
87 };
88 };
89
90 /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */
91 three_pwm_pins: three-pwm-pins {
92 mux {
93 function = "pwm";
94 groups = "pwm0_1", "pwm1_0", "pwm2";
95 };
96 };
97
98 mmc0_pins_default: mmc0default {
99 mux {
100 function = "flash";
101 groups = "emmc_45";
102 };
103 conf-cmd-dat {
104 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
105 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
106 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
107 input-enable;
108 drive-strength = <MTK_DRIVE_4mA>;
109 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
110 };
111 conf-clk {
112 pins = "SPI1_CS";
113 drive-strength = <MTK_DRIVE_6mA>;
114 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
115 };
116 conf-rst {
117 pins = "PWM0";
118 drive-strength = <MTK_DRIVE_4mA>;
119 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
120 };
121 };
122};
123
124&pwm {
125 pinctrl-names = "default";
126 pinctrl-0 = <&two_pwm_pins>;
127 status = "okay";
128};
129
130&watchdog {
131 status = "disabled";
132};
133
134&mmc0 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&mmc0_pins_default>;
137 bus-width = <4>;
138 max-frequency = <52000000>;
139 cap-sd-highspeed;
140 r_smpl = <0>;
141 vmmc-supply = <&reg_3p3v>;
142 vqmmc-supply = <&reg_3p3v>;
143 status = "okay";
144};