blob: 235bc480c7fec6cd905944bfcffa8ca27f373311 [file] [log] [blame]
wdenk3bbc8992003-12-07 22:27:15 +00001/*
2 * (C) Copyright 2003
3 * MuLogic B.V.
4 *
5 * (C) Copyright 2002
6 * Simple Network Magic Corporation
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* various debug settings */
38#undef CFG_DEVICE_NULLDEV /* null device */
39#undef CONFIG_SILENT_CONSOLE /* silent console */
40#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
41#undef DEBUG /* debug output code */
42#undef DEBUG_FLASH /* debug flash code */
43#undef FLASH_DEBUG /* debug fash code */
44#undef DEBUG_ENV /* debug environment code */
45
46#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
47#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
48
49/*
50 * High Level Configuration Options
51 * (easy to change)
52 */
53#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
54#define CONFIG_QS823 1 /* ...on a QS823 module */
55#define CONFIG_SCC2_ENET 1 /* SCC2 10BaseT ethernet */
56
57/* Select the target clock speed */
58#undef CONFIG_CLOCK_16MHZ /* cpu=16,777,216 Hz, mem=16Mhz */
59#undef CONFIG_CLOCK_33MHZ /* cpu=33,554,432 Hz, mem=33Mhz */
60#undef CONFIG_CLOCK_50MHZ /* cpu=49,971,200 Hz, mem=33Mhz */
61#define CONFIG_CLOCK_66MHZ 1 /* cpu=67,108,864 Hz, mem=66Mhz */
62#undef CONFIG_CLOCK_80MHZ /* cpu=79,986,688 Hz, mem=33Mhz */
63
64#ifdef CONFIG_CLOCK_16MHZ
65#define CONFIG_CLOCK_MULT 512
66#endif
67
68#ifdef CONFIG_CLOCK_33MHZ
69#define CONFIG_CLOCK_MULT 1024
70#endif
71
72#ifdef CONFIG_CLOCK_50MHZ
73#define CONFIG_CLOCK_MULT 1525
74#endif
75
76#ifdef CONFIG_CLOCK_66MHZ
77#define CONFIG_CLOCK_MULT 2048
78#endif
79
80#ifdef CONFIG_CLOCK_80MHZ
81#define CONFIG_CLOCK_MULT 2441
82#endif
83
84/* choose flash size, 4Mb or 8Mb */
85#define CONFIG_FLASH_4MB 1 /* board has 4Mb flash */
86#undef CONFIG_FLASH_8MB /* board has 8Mb flash */
87
88#define CONFIG_CLOCK_BASE 32768 /* Base clock input freq */
89
90#undef CONFIG_8xx_CONS_SMC1
91#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
92#undef CONFIG_8xx_CONS_NONE
93
94#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
95
96#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
97
98/* Define default IP addresses */
99#define CONFIG_IPADDR 192.168.1.99 /* own ip address */
100#define CONFIG_SERVERIP 192.168.1.19 /* used for tftp (not nfs?) */
101
102/* message to say directly after booting */
103#define CONFIG_PREBOOT "echo '';" \
104 "echo 'type:';" \
105 "echo 'run boot_nfs to boot to NFS';" \
106 "echo 'run boot_flash to boot to flash';" \
107 "echo '';" \
108 "echo 'run flash_rootfs to install a new rootfs';" \
109 "echo 'run flash_env to clear the env sector';" \
110 "echo 'run flash_rw to clear the rw fs';" \
111 "echo 'run flash_uboot to install a new u-boot';" \
112 "echo 'run flash_kernel to install a new kernel';"
113
114/* wait 5 seconds before executing CONFIG_BOOTCOMMAND */
115#define CONFIG_BOOTDELAY 5
116#define CONFIG_BOOTCOMMAND "run boot_nfs"
117
118#undef CONFIG_BOOTARGS /* made by set_nfs of set_flash */
119
120/* Our flash filesystem looks like this
121 *
122 * 4Mb board:
123 * ffc0 0000 - ffeb ffff root filesystem (jffs2) (~3Mb)
124 * ffec 0000 - ffed ffff read-write filesystem (ext2)
125 * ffee 0000 - ffef ffff environment
126 * fff0 0000 - fff1 ffff u-boot
127 * fff2 0000 - ffff ffff linux kernel
128 *
129 * 8Mb board:
130 * ff80 0000 - ffeb ffff root filesystem (jffs2) (~7Mb)
131 * ffec 0000 - ffed ffff read-write filesystem (ext2)
132 * ffee 0000 - ffef ffff environment
133 * fff0 0000 - fff1 ffff u-boot
134 * fff2 0000 - ffff ffff linux kernel
135 *
136 */
137
138/* environment for 4Mb board */
139#ifdef CONFIG_FLASH_4MB
140#define CONFIG_EXTRA_ENV_SETTINGS \
141 "serial#=QS823\0" \
142 "hostname=qs823\0" \
143 "netdev=eth0\0" \
144 "ethaddr=00:01:02:B4:36:56\0" \
145 "rootpath=/exports/rootfs\0" \
146 "mtdparts=mtdparts=phys:2816k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
147 /* fill in variables */ \
148 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
149 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
150 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
151 /* commands */ \
152 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
153 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
154 /* reinstall flash parts */ \
155 "flash_rootfs=protect off ffc00000 ffebffff; era ffc00000 ffebffff; tftp ffc00000 /tftpboot/rootfs.jffs2\0" \
156 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
157 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
158 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.4mb.bin\0" \
159 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
160#endif /* CONFIG_FLASH_4MB */
161
162/* environment for 8Mb board */
163#ifdef CONFIG_FLASH_8MB
164#define CONFIG_EXTRA_ENV_SETTINGS \
165 "serial#=QS823\0" \
166 "hostname=qs823\0" \
167 "netdev=eth0\0" \
168 "ethaddr=00:01:02:B4:36:56\0" \
169 "rootpath=/exports/rootfs\0" \
170 "mtdparts=mtdparts=phys:6912k(root),128k(rw),128k(env),128k(u-boot),-(kernel)\0" \
171 /* fill in variables */ \
172 "set_ip=setenv ip ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off\0" \
173 "set_nfs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath $ip init=/sbin/init $mtdparts\0" \
174 "set_flash=setenv bootargs root=/dev/mtdblock1 ro $ip init=/sbin/init $mtdparts\0" \
175 /* commands */ \
176 "boot_nfs=run set_ip; run set_nfs; tftp 0x400000 /tftpboot/vmlinux.UBoot; bootm 0x400000\0" \
177 "boot_flash=run set_ip; run set_flash; bootm fff20000\0" \
178 /* reinstall flash parts */ \
179 "flash_rootfs=protect off ff800000 ffebffff; era ff800000 ffebffff; tftp ff800000 /tftpboot/rootfs.jffs2\0" \
180 "flash_rw=protect off ffec0000 ffedffff; era ffec0000 ffedffff\0" \
181 "flash_env=protect off ffee0000 ffefffff; era ffee0000 ffefffff\0" \
182 "flash_uboot=protect off fff00000 fff1ffff; era fff00000 fff1ffff; tftp fff00000 /tftpboot/u-boot.8mb.bin\0" \
183 "flash_kernel=protect off fff20000 ffffffff; era fff20000 ffffffff; tftp fff20000 /tftpboot/vmlinux.UBoot\0"
184#endif /* CONFIG_FLASH_8MB */
185
186#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
187#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
188#undef CONFIG_WATCHDOG /* watchdog disabled */
189#undef CONFIG_STATUS_LED /* Status LED disabled */
190#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
191
192#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
193
194#undef CONFIG_MAC_PARTITION
195#undef CONFIG_DOS_PARTITION
196
197#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
198
199#define CONFIG_COMMANDS (CFG_CMD_BDI | \
200 CFG_CMD_BOOTD | \
201 CFG_CMD_CONSOLE | \
202 CFG_CMD_DATE | \
203 CFG_CMD_ENV | \
204 CFG_CMD_FLASH | \
205 CFG_CMD_IMI | \
206 CFG_CMD_IMMAP | \
207 CFG_CMD_MEMORY | \
208 CFG_CMD_NET | \
209 CFG_CMD_RUN)
210
211/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
212#include <cmd_confdefs.h>
213
214/*-----------------------------------------------------------------------
215 * Environment variable storage is in FLASH, one sector before U-boot
216 */
217#define CFG_ENV_IS_IN_FLASH 1
218#define CFG_ENV_SECT_SIZE 0x20000 /* 128Kb, one whole sector */
219#define CFG_ENV_SIZE 0x2000 /* 8kb */
220#define CFG_ENV_ADDR 0xffee0000 /* address of env sector */
221
222/*-----------------------------------------------------------------------
223 * Miscellaneous configurable options
224 */
225#define CFG_LONGHELP /* undef to save memory */
226#define CFG_PROMPT "=> " /* Monitor Command Prompt */
227
228#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
229#define CFG_PROMPT_HUSH_PS2 "> "
230
231#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
232#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
233#else
234#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
235#endif
236#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
237#define CFG_MAXARGS 16 /* max number of command args */
238#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
239
240#define CFG_MEMTEST_START 0x0400000 /* memtest works */
241#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
242
243#define CFG_LOAD_ADDR 0x400000 /* default load address */
244
245#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
246
247#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
248
249/*-----------------------------------------------------------------------
250 * Low Level Configuration Settings
251 * (address mappings, register initial values, etc.)
252 * You should know what you are doing if you make changes here.
253 */
254
255/*-----------------------------------------------------------------------
256 * Internal Memory Mapped Register
257 */
258#define CFG_IMMR 0xFF000000
259
260/*-----------------------------------------------------------------------
261 * Definitions for initial stack pointer and data area (in DPRAM)
262 */
263#define CFG_INIT_RAM_ADDR CFG_IMMR
264#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
265#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
266#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
267#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
268
269/*-----------------------------------------------------------------------
270 * Start addresses for the final memory configuration
271 * (Set up by the startup code)
272 * Please note that CFG_SDRAM_BASE _must_ start at 0
273 */
274#define CFG_SDRAM_BASE 0x00000000
275#define CFG_FLASH_BASE 0xFF800000 /* Allow an 8Mbyte window */
276
277#define FLASH_BASE0_4M_PRELIM 0xFFC00000 /* Base for 4M Flash */
278#define FLASH_BASE0_8M_PRELIM 0xFF800000 /* Base for 8M Flash */
279
280#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
281#define CFG_MONITOR_BASE 0xFFF00000 /* U-boot location */
282#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
283
284/*
285 * For booting Linux, the board info and command line data
286 * have to be in the first 8 MB of memory, since this is
287 * the maximum mapped by the Linux kernel during initialization.
288 */
289#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
290
291/*-----------------------------------------------------------------------
292 * TODO flash parameters
293 * FLASH organization for Intel Strataflash
294 */
295#undef CFG_FLASH_16BIT /* 32-bit wide flash memory */
296#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
297#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
298
299#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
300#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
301
302/*-----------------------------------------------------------------------
303 * Cache Configuration
304 */
305#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
306#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
307#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
308#endif
309
310/*-----------------------------------------------------------------------
311 * SYPCR - System Protection Control 11-9
312 * SYPCR can only be written once after reset!
313 *-----------------------------------------------------------------------
314 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
315 */
316
317#ifdef CONFIG_WATCHDOG
318#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
319#else
320#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
321#endif
322
323/*-----------------------------------------------------------------------
324 * SIUMCR - SIU Module Configuration 11-6
325 *-----------------------------------------------------------------------
326 */
327#define CFG_SIUMCR (SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)
328
329/*-----------------------------------------------------------------------
330 * TBSCR - Time Base Status and Control 11-26
331 *-----------------------------------------------------------------------
332 */
333#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
334
335/*-----------------------------------------------------------------------
336 * RTCSC - Real-Time Clock Status and Control Register 11-27
337 *-----------------------------------------------------------------------
338 */
339#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
340
341/*-----------------------------------------------------------------------
342 * PISCR - Periodic Interrupt Status and Control 11-31
343 *-----------------------------------------------------------------------
344 */
345#define CFG_PISCR (PISCR_PS | PISCR_PITF)
346
347/*-----------------------------------------------------------------------
348 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
349 *-----------------------------------------------------------------------
350 */
351
352/* MF (Multiplication Factor of SPLL) */
353/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */
354#define vPLPRCR_MF ((CONFIG_CLOCK_MULT+1) << 20)
355#define CFG_PLPRCR (vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)
356
357/*-----------------------------------------------------------------------
358 * SCCR - System Clock and reset Control Register 15-27
359 *-----------------------------------------------------------------------
360 */
361#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
362#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
363#define CFG_BRGCLK_PRESCALE 1
364#endif
365
366#if defined(CONFIG_CLOCK_66MHZ)
367#define CFG_SCCR (SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
368#define CFG_BRGCLK_PRESCALE 4
369#endif
370
371#if defined(CONFIG_CLOCK_80MHZ)
372#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
373#define CFG_BRGCLK_PRESCALE 4
374#endif
375
376#define SCCR_MASK CFG_SCCR
377
378/*-----------------------------------------------------------------------
379 * Debug Enable Register
380 * 0x73E67C0F - All interrupts handled by BDM
381 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
382 *-----------------------------------------------------------------------
383#define CFG_DER 0x73E67C0F
384#define CFG_DER 0x0082400F
385
386 #-------------------------------------------------------------------------
387 # Program the Debug Enable Register (DER). This register provides the user
388 # with the reason for entering into the debug mode. We want all conditions
389 # to end up as an exception. We don't want to enter into debug mode for
390 # any condition. See the back of of the Development Support section of the
391 # MPC860 User Manual for a description of this register.
392 #-------------------------------------------------------------------------
393*/
394#define CFG_DER 0
395
396/*-----------------------------------------------------------------------
397 * Memory Controller Initialization Constants
398 *-----------------------------------------------------------------------
399 */
400
401/*
402 * BR0 and OR0 (AMD dual FLASH devices)
403 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
404 */
405#define CFG_PRELIM_OR_AM
406#define CFG_OR_TIMING_FLASH
407
408/*
409 *-----------------------------------------------------------------------
410 * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
411 * flash that resides on the QS823.
412 *-----------------------------------------------------------------------
413 */
414
415/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
416/* represents a minumum 32K block size. */
417#define vBR0_BA ((0xFF80 << 16) + (0 << 15))
418#define CFG_BR0_PRELIM (vBR0_BA | BR_V)
419
420/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits */
421/* which defines a 8 Mbyte memory block. */
422#define vOR0_AM ((0xFF80 << 16) + (0 << 15))
423
424#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
425/* 0101 = Add a 5 clock cycle wait state */
426#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
427#endif
428
429#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
430/* 0011 = Add a 3 clock cycle wait state */
431/* 29.8ns clock * (3 + 2) = 149ns cycle time */
432#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
433#endif
434
435#if defined(CONFIG_CLOCK_16MHZ)
436/* 0010 = Add a 2 clock cycle wait state */
437#define CFG_OR0_PRELIM (vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
438#endif
439
440/*
441 * BR1 and OR1 (SDRAM)
442 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
443 * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
444 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
445 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
446 */
447
448#define SDRAM_BASE 0x00000000 /* SDRAM bank */
449#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
450
451/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
452 * represents a 128 Mbyte block the DRAM in
453 * this address base.
454 */
455#define vOR1_AM ((0xF800 << 16) + (0 << 15))
456#define vBR1_BA ((0x0000 << 16) + (0 << 15))
457#define CFG_OR1 (vOR1_AM | OR_CSNT_SAM | OR_BI)
458#define CFG_BR1 (vBR1_BA | BR_MS_UPMA | BR_V)
459
460/* Machine A Mode Register */
461
462/* PTA Periodic Timer A */
463
464#if defined(CONFIG_CLOCK_80MHZ)
465#define vMAMR_PTA (19 << 24)
466#endif
467
468#if defined(CONFIG_CLOCK_66MHZ)
469#define vMAMR_PTA (16 << 24)
470#endif
471
472#if defined(CONFIG_CLOCK_50MHZ)
473#define vMAMR_PTA (195 << 24)
474#endif
475
476#if defined(CONFIG_CLOCK_33MHZ)
477#define vMAMR_PTA (131 << 24)
478#endif
479
480#if defined(CONFIG_CLOCK_16MHZ)
481#define vMAMR_PTA (65 << 24)
482#endif
483
484/* For boards with 16M of SDRAM */
485#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
486#define CFG_16M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
487MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
488
489/* For boards with 32M of SDRAM */
490#define SDRAM_32M_MAX_SIZE 0x02000000 /* max 32MB SDRAM */
491#define CFG_32M_MAMR (vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
492MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
493
494
495/* Memory Periodic Timer Prescaler Register */
496
497#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
498/* Divide by 32 */
499#define CFG_MPTPR 0x02
500#endif
501
502#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
503/* Divide by 16 */
504#define CFG_MPTPR 0x04
505#endif
506
507/*
508 * BR2 and OR2 (Unused)
509 * Base address = 0xF020_0000 - 0xF020_0FFF
510 *
511 */
512#define CFG_OR2_PRELIM 0xFFF00000
513#define CFG_BR2_PRELIM 0xF0200000
514
515/*
516 * BR3 and OR3 (External Bus CS3)
517 * Base address = 0xF030_0000 - 0xF030_0FFF
518 *
519 */
520#define CFG_OR3_PRELIM 0xFFF00000
521#define CFG_BR3_PRELIM 0xF0300000
522
523/*
524 * BR4 and OR4 (External Bus CS3)
525 * Base address = 0xF040_0000 - 0xF040_0FFF
526 *
527 */
528#define CFG_OR4_PRELIM 0xFFF00000
529#define CFG_BR4_PRELIM 0xF0400000
530
531
532/*
533 * BR4 and OR4 (External Bus CS3)
534 * Base address = 0xF050_0000 - 0xF050_0FFF
535 *
536 */
537#define CFG_OR5_PRELIM 0xFFF00000
538#define CFG_BR5_PRELIM 0xF0500000
539
540/*
541 * BR6 and OR6 (Unused)
542 * Base address = 0xF060_0000 - 0xF060_0FFF
543 *
544 */
545#define CFG_OR6_PRELIM 0xFFF00000
546#define CFG_BR6_PRELIM 0xF0600000
547
548/*
549 * BR7 and OR7 (Unused)
550 * Base address = 0xF070_0000 - 0xF070_0FFF
551 *
552 */
553#define CFG_OR7_PRELIM 0xFFF00000
554#define CFG_BR7_PRELIM 0xF0700000
555
556/*
557 * Internal Definitions
558 *
559 * Boot Flags
560 */
561#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
562#define BOOTFLAG_WARM 0x02 /* Software reboot */
563
564/*
565 * Sanity checks
566 */
567#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
568#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
569#endif
570
571#endif /* __CONFIG_H */