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wdenk5e5f9ed2005-04-13 23:15:10 +00001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
34#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
35
36#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37
38#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39#define BOOTFLAG_WARM 0x02 /* Software reboot */
40
41#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
42#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
43# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
44#endif
45
46#define CONFIG_BOARD_EARLY_INIT_R
47
48/*
49 * Serial console configuration
50 */
51#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
53#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
54
55/*
56 * Supported commands
57 */
58#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
59 CFG_CMD_ASKENV | \
60 CFG_CMD_DATE | \
61 CFG_CMD_DHCP | \
62 CFG_CMD_IMMAP | \
63 CFG_CMD_MII | \
64 CFG_CMD_NFS | \
65 CFG_CMD_REGINFO | \
66 CFG_CMD_SNTP )
67
68/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
69#include <cmd_confdefs.h>
70
71/*
72 * MUST be low boot - HIGHBOOT is not supported anymore
73 */
74#if (TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
75# define CFG_LOWBOOT 1
76# define CFG_LOWBOOT16 1
77#else
78# error "TEXT_BASE must be 0xFE000000"
79#endif
80
81/*
82 * Autobooting
83 */
84#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
85
86#define CONFIG_PREBOOT "echo;" \
87 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
88 "echo"
89
90#undef CONFIG_BOOTARGS
91
92#define CONFIG_EXTRA_ENV_SETTINGS \
93 "netdev=eth0\0" \
94 "nfsargs=setenv bootargs root=/dev/nfs rw " \
95 "nfsroot=$(serverip):$(rootpath)\0" \
96 "ramargs=setenv bootargs root=/dev/ram rw\0" \
97 "addip=setenv bootargs $(bootargs) " \
98 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
99 ":$(hostname):$(netdev):off panic=1\0" \
100 "flash_nfs=run nfsargs addip;" \
101 "bootm $(kernel_addr)\0" \
102 "flash_self=run ramargs addip;" \
103 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
104 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
105 "rootpath=/opt/eldk/ppc_6xx\0" \
106 "bootfile=/tftpboot/canmb/uImage\0" \
107 ""
108
109#define CONFIG_BOOTCOMMAND "run flash_self"
110
111/*
112 * IPB Bus clocking configuration.
113 */
114#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
115
116/*
117 * Flash configuration, expect one 16 Megabyte Bank at most
118 */
119#define CFG_FLASH_BASE 0xFE000000
120#define CFG_FLASH_SIZE 0x02000000
121#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
122#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
123
124#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
125#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
126
127#define CFG_FLASH_CFI_DRIVER
128#define CFG_FLASH_CFI
129#define CFG_FLASH_EMPTY_INFO
130
131/*
wdenk5e5f9ed2005-04-13 23:15:10 +0000132 * Environment settings
133 */
134#define CFG_ENV_IS_IN_FLASH 1
135#define CFG_ENV_OFFSET (2*128*1024)
136#define CFG_ENV_SIZE 0x2000
137#define CFG_ENV_SECT_SIZE (128*1024)
138
139/*
140 * Memory map
141 *
142 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
143 */
144#define CFG_MBAR 0xf0000000 /* DO NOT CHANGE this */
145#define CFG_SDRAM_BASE 0x00000000
146#define CFG_DEFAULT_MBAR 0x80000000
147
148/* Use SRAM until RAM will be available */
149#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
150#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
151
152
153#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
154#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
155#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
156
157#define CFG_MONITOR_BASE TEXT_BASE
158#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
159# define CFG_RAMBOOT 1
160#endif
161
162#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
163#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
164#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
165
166/*
167 * Ethernet configuration
168 */
169#define CONFIG_MPC5xxx_FEC 1
wdenka6310922005-04-21 21:10:22 +0000170#define CONFIG_PHY_ADDR 0x0
wdenk5e5f9ed2005-04-13 23:15:10 +0000171/*
172 * GPIO configuration:
173 * PSC1,2,3 predefined as UART
174 * PCI disabled
175 * Ethernet 100 with MD
176 */
177#define CFG_GPS_PORT_CONFIG 0x00058444
178
179/*
180 * Miscellaneous configurable options
181 */
182#define CFG_LONGHELP /* undef to save memory */
183#define CFG_PROMPT "=> " /* Monitor Command Prompt */
184#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
185# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
186#else
187# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
188#endif
189#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
190#define CFG_MAXARGS 16 /* max number of command args */
191#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
192
193#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
194#define CFG_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
195
196#define CFG_LOAD_ADDR 0x200000 /* default load address */
197
198#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
199
200#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
201
202/*
203 * Various low-level settings
204 */
205#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
206#define CFG_HID0_FINAL HID0_ICE
207
208#define CFG_BOOTCS_START CFG_FLASH_BASE
209#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
210#define CFG_BOOTCS_CFG 0x00047D01
211#define CFG_CS0_START CFG_FLASH_BASE
212#define CFG_CS0_SIZE CFG_FLASH_SIZE
213
214#define CFG_CS_BURST 0x00000000
215#define CFG_CS_DEADCYCLE 0x33333333
216
217#define CFG_RESET_ADDRESS 0x7f000000
218
219#endif /* __CONFIG_H */