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Valentin Yakovenkov446707c2009-10-26 18:43:04 -04001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for BF561 Acvilon System On Module
Valentin Yakovenkov446707c2009-10-26 18:43:04 -04003 * For more information please go to http://www.niistt.ru/
4 */
5
6#ifndef __CONFIG_BF561_ACVILON_H__
7#define __CONFIG_BF561_ACVILON_H__
8
9#include <asm/config-pre.h>
10
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040011/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf561-0.5
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040016
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040017/*
18 * Clock Settings
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
21 */
22/* CONFIG_CLKIN_HZ is any value in Hz */
23#define CONFIG_CLKIN_HZ 12000000
24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
25/* 1 = CLKIN / 2 */
26#define CONFIG_CLKIN_HALF 0
27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
28/* 1 = bypass PLL */
29#define CONFIG_PLL_BYPASS 0
30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31/* Values can range from 0-63 (where 0 means 64) */
32#define CONFIG_VCO_MULT 50
33/* CCLK_DIV controls the core clock divider */
34/* Values can be 1, 2, 4, or 8 ONLY */
35#define CONFIG_CCLK_DIV 1
36/* SCLK_DIV controls the system clock divider */
37/* Values can range from 1-15 */
38#define CONFIG_SCLK_DIV 5
39
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040040/*
41 * Memory Settings
42 */
43#define CONFIG_MEM_ADD_WDTH 10
44#define CONFIG_MEM_SIZE 128
45
46#define CONFIG_EBIU_SDRRC_VAL 0x300
47#define CONFIG_EBIU_SDGCTL_VAL 0x00B11189
48
49#define CONFIG_EBIU_AMGCTL_VAL 0x4e
50#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
51#define CONFIG_EBIU_AMBCTL1_VAL 0x99b35554
52
Sonic Zhang6e6b2212013-12-09 12:45:29 +080053#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040054#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
55
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040056/*
57 * RTC Settings
58 */
59#define CONFIG_RTC_DS1337
60#define CONFIG_SYS_I2C_RTC_ADDR 0x68
61
62/* I2C SYSMON (LM75, AD7414 is almost compatible) */
63#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
64#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
65#define CONFIG_SYS_I2C_DTT_ADDR 0x49
66/*#define CONFIG_SYS_DTT_MAX_TEMP 70
67#define CONFIG_SYS_DTT_LOW_TEMP -30
68#define CONFIG_SYS_DTT_HYSTERESIS 3*/
69
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040070/*
71 * Network Settings
72 */
73#define ADI_CMDS_NETWORK 1
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040074#define CONFIG_CMD_DATE
75#define CONFIG_CMD_DTT
76
77#if defined(CONFIG_CMD_NET)
78
79#define CONFIG_SMC911X 1
80#define CONFIG_SMC911X_32_BIT
81/* #define CONFIG_SMC911X_16_BIT */
82#define CONFIG_SMC911X_BASE 0x28000000
83
84#endif /* (CONFIG_CMD_NET) */
85
86#define CONFIG_HOSTNAME bf561-acvilon
87
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040088/*
89 * Flash Settings
90 */
91#define CONFIG_SYS_NO_FLASH
92
Valentin Yakovenkov446707c2009-10-26 18:43:04 -040093/*
94 * I2C Settings
95 */
96#define CONFIG_HARD_I2C
97/* Use 300kHz speed by default */
98#define CONFIG_SYS_I2C_SPEED 0x00
99#define CONFIG_PCA9564_I2C
100#define CONFIG_PCA9564_BASE 0x2c000000
101
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400102/*
103 * SPI Settings
104 */
105#define CONFIG_BFIN_SPI
106#define CONFIG_ENV_SPI_MAX_HZ 10000000
107#define CONFIG_SF_DEFAULT_SPEED 10000000
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400108
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400109/*
110 * Env Storage Settings
111 */
112#define CONFIG_ENV_IS_IN_SPI_FLASH
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400113#define CONFIG_ENV_SECT_SIZE (1056 * 8)
114#define CONFIG_ENV_OFFSET ((16 + 256) * 1056)
115#define CONFIG_ENV_SIZE (8 * 1056)
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400116
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400117/*
118 * NAND Settings
119 * We're using NAND_PLAT driver to make things simplier
120 */
121#define CONFIG_NAND_PLAT
122#define CONFIG_CMD_NAND
123#define CONFIG_SYS_NAND_BASE 0x24000000
124#define CONFIG_SYS_MAX_NAND_DEVICE 1
125
126#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
127#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400128#define BFIN_NAND_WRITE(addr, cmd) \
129 do { \
130 bfin_write8(addr, cmd); \
131 SSYNC(); \
132 } while (0)
133
134#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
135#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400136#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400137
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400138/*
139 * Misc Settings
140 */
141#define CONFIG_UART_CONSOLE 0
142#define CONFIG_BAUDRATE 57600
Valentin Yakovenkov446707c2009-10-26 18:43:04 -0400143
144/*
145 * Pull in common ADI header for remaining command/environment setup
146 */
147#include <configs/bfin_adi_common.h>
148
149#endif /* __CONFIG_BF561_ACVILON_H__ */