blob: 6046ab789525d8bb975aa7d7fea45fca9130d0f3 [file] [log] [blame]
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +05301/*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __LS1012ARDB_H__
8#define __LS1012ARDB_H__
9
10#include "ls1012a_common.h"
11
12
13#define CONFIG_DIMM_SLOTS_PER_CTLR 1
14#define CONFIG_CHIP_SELECTS_PER_CTRL 1
15#define CONFIG_NR_DRAM_BANKS 2
16#define CONFIG_SYS_SDRAM_SIZE 0x40000000
17
18#define CONFIG_SYS_MMDC_CORE_CONTROL_1 0x05180000
19#define CONFIG_SYS_MMDC_CORE_CONTROL_2 0x85180000
20
21#define CONFIG_CMD_MEMINFO
22#define CONFIG_CMD_MEMTEST
23#define CONFIG_SYS_MEMTEST_START 0x80000000
24#define CONFIG_SYS_MEMTEST_END 0x9fffffff
25
26/*
27* USB
28*/
29#define CONFIG_HAS_FSL_XHCI_USB
30
31#ifdef CONFIG_HAS_FSL_XHCI_USB
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053032#define CONFIG_USB_XHCI_FSL
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053033#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
34#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
35#define CONFIG_USB_STORAGE
36#endif
37
38/*
39 * I2C IO expander
40 */
41
42#define I2C_MUX_IO1_ADDR 0x24
43#define __SW_BOOT_MASK 0xFC
44#define __SW_BOOT_EMU 0x10
45#define __SW_BOOT_BANK1 0x00
46#define __SW_BOOT_BANK2 0x01
47#define __SW_REV_MASK 0x07
48#define __SW_REV_A 0xF8
49#define __SW_REV_B 0xF0
50
51/* MMC */
52#define CONFIG_MMC
53#ifdef CONFIG_MMC
54#define CONFIG_FSL_ESDHC
55#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
56#define CONFIG_GENERIC_MMC
57#define CONFIG_DOS_PARTITION
58#endif
59
60/* SATA */
61#define CONFIG_LIBATA
62#define CONFIG_SCSI
63#define CONFIG_SCSI_AHCI
64#define CONFIG_SCSI_AHCI_PLAT
65#define CONFIG_CMD_SCSI
66#define CONFIG_DOS_PARTITION
67#define CONFIG_BOARD_LATE_INIT
68
69#define CONFIG_SYS_SATA AHCI_BASE_ADDR
70
71#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
72#define CONFIG_SYS_SCSI_MAX_LUN 1
73#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
74 CONFIG_SYS_SCSI_MAX_LUN)
75#define CONFIG_PCI /* Enable PCI/PCIE */
76#define CONFIG_PCIE1 /* PCIE controller 1 */
77#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
78#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
79
80#define CONFIG_SYS_PCI_64BIT
81
82#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
83#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
84#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
85#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
86
87#define CONFIG_SYS_PCIE_IO_BUS 0x00000000
88#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
89#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
90
91#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
92#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
93#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */
94
95#define CONFIG_NET_MULTI
96#define CONFIG_PCI_PNP
97#define CONFIG_PCI_SCAN_SHOW
98#define CONFIG_CMD_PCI
99
100#define CONFIG_CMD_MEMINFO
101#define CONFIG_CMD_MEMTEST
102#define CONFIG_SYS_MEMTEST_START 0x80000000
103#define CONFIG_SYS_MEMTEST_END 0x9fffffff
104
105#endif /* __LS1012ARDB_H__ */