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wdenk6c7a1402004-07-11 19:17:20 +00001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@freescale.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
29
30#include "sdram.h"
31
32#ifndef CFG_RAMBOOT
33static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
34{
35 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
36
37 /* unlock mode register */
38 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000000 | hi_addr_bit;
39 __asm__ volatile ("sync");
40
41 /* precharge all banks */
42 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
43 __asm__ volatile ("sync");
44
45 if (sdram_conf->ddr) {
46 /* set mode register: extended mode */
47 *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->emode;
48 __asm__ volatile ("sync");
49
50 /* set mode register: reset DLL */
51 *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode | 0x04000000;
52 __asm__ volatile ("sync");
53 }
54
55 /* precharge all banks */
56 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000002 | hi_addr_bit;
57 __asm__ volatile ("sync");
58
59 /* auto refresh */
60 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | 0x80000004 | hi_addr_bit;
61 __asm__ volatile ("sync");
62
63 /* set mode register */
64 *(vu_long *)MPC5XXX_SDRAM_MODE = sdram_conf->mode;
65 __asm__ volatile ("sync");
66
67 /* normal operation */
68 *(vu_long *)MPC5XXX_SDRAM_CTRL = sdram_conf->control | hi_addr_bit;
69 __asm__ volatile ("sync");
70}
71#endif
72
73/*
74 * ATTENTION: Although partially referenced initdram does NOT make real use
75 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
76 * is something else than 0x00000000.
77 */
78
79#if defined(CONFIG_MPC5200)
80long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
81{
82 ulong dramsize = 0;
83 ulong dramsize2 = 0;
84#ifndef CFG_RAMBOOT
85 ulong test1, test2;
86
87 /* setup SDRAM chip selects */
88 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
89 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
90 __asm__ volatile ("sync");
91
92 /* setup config registers */
93 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
94 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
95 __asm__ volatile ("sync");
96
97 if (sdram_conf->ddr) {
98 /* set tap delay */
99 *(vu_long *)MPC5XXX_CDM_PORCFG = sdram_conf->tapdelay;
100 __asm__ volatile ("sync");
101 }
102
103 /* find RAM size using SDRAM CS0 only */
104 mpc5xxx_sdram_start(sdram_conf, 0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200105 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenk6c7a1402004-07-11 19:17:20 +0000106 mpc5xxx_sdram_start(sdram_conf, 1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200107 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenk6c7a1402004-07-11 19:17:20 +0000108 if (test1 > test2) {
109 mpc5xxx_sdram_start(sdram_conf, 0);
110 dramsize = test1;
111 } else {
112 dramsize = test2;
113 }
114
115 /* memory smaller than 1MB is impossible */
116 if (dramsize < (1 << 20)) {
117 dramsize = 0;
118 }
119
120 /* set SDRAM CS0 size according to the amount of RAM found */
121 if (dramsize > 0) {
122 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
123 } else {
124 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
125 }
126
127 /* let SDRAM CS1 start right after CS0 */
128 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
129
130 /* find RAM size using SDRAM CS1 only */
131 mpc5xxx_sdram_start(sdram_conf, 0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200132 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenk6c7a1402004-07-11 19:17:20 +0000133 mpc5xxx_sdram_start(sdram_conf, 1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200134 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenk6c7a1402004-07-11 19:17:20 +0000135 if (test1 > test2) {
136 mpc5xxx_sdram_start(sdram_conf, 0);
137 dramsize2 = test1;
138 } else {
139 dramsize2 = test2;
140 }
141
142 /* memory smaller than 1MB is impossible */
143 if (dramsize2 < (1 << 20)) {
144 dramsize2 = 0;
145 }
146
147 /* set SDRAM CS1 size according to the amount of RAM found */
148 if (dramsize2 > 0) {
149 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
150 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
151 } else {
152 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
153 }
154
155#else /* CFG_RAMBOOT */
156
157 /* retrieve size of memory connected to SDRAM CS0 */
158 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
159 if (dramsize >= 0x13) {
160 dramsize = (1 << (dramsize - 0x13)) << 20;
161 } else {
162 dramsize = 0;
163 }
164
165 /* retrieve size of memory connected to SDRAM CS1 */
166 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
167 if (dramsize2 >= 0x13) {
168 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
169 } else {
170 dramsize2 = 0;
171 }
172
173#endif /* CFG_RAMBOOT */
174
175 return dramsize + dramsize2;
176}
177
178#elif defined(CONFIG_MGT5100)
179
180long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
181{
182 ulong dramsize = 0;
183#ifndef CFG_RAMBOOT
184 ulong test1, test2;
185
186 /* setup and enable SDRAM chip selects */
187 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
188 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
189 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
190 __asm__ volatile ("sync");
191
192 /* setup config registers */
193 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = sdram_conf->config1;
194 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = sdram_conf->config2;
195
196 /* address select register */
197 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = sdram_conf->addrsel;
198 __asm__ volatile ("sync");
199
200 /* find RAM size */
201 mpc5xxx_sdram_start(sdram_conf, 0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200202 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenk6c7a1402004-07-11 19:17:20 +0000203 mpc5xxx_sdram_start(sdram_conf, 1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200204 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenk6c7a1402004-07-11 19:17:20 +0000205 if (test1 > test2) {
206 mpc5xxx_sdram_start(sdram_conf, 0);
207 dramsize = test1;
208 } else {
209 dramsize = test2;
210 }
211
212 /* set SDRAM end address according to size */
213 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
214
215#else /* CFG_RAMBOOT */
216
217 /* Retrieve amount of SDRAM available */
218 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
219
220#endif /* CFG_RAMBOOT */
221
222 return dramsize;
223}
224
225#else
226#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
227#endif