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dzu@denx.de6ca24c62006-04-21 18:30:47 +02001/*
2 * -- Version 1.1 --
3 *
4 * (C) Copyright 2003-2005
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004-2005
8 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
9 *
10 * (C) Copyright 2005
11 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
12 *
13 * History:
14 * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38/*
39 * High Level Configuration Options
40 */
41#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
42#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
43#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
44
Wolfgang Denk610cf362006-05-03 01:24:04 +020045#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
46#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
47#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020048#define CONFIG_BC3450_USB 1 /* + USB support */
49# define CONFIG_FAT 1 /* + FAT support */
50# define CONFIG_EXT2 1 /* + EXT2 support */
51#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
52#undef CONFIG_BC3450_CAN /* + CAN transceiver */
53#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
Wolfgang Denk610cf362006-05-03 01:24:04 +020054#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
55#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020056#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
57#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
58
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020060
61#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
62#define BOOTFLAG_WARM 0x02 /* Software reboot */
63
Becky Bruce31d82672008-05-08 19:02:12 -050064#define CONFIG_HIGH_BATS 1 /* High BATs supported */
65
dzu@denx.de6ca24c62006-04-21 18:30:47 +020066/*
67 * Serial console configuration
68 */
69#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
70#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
dzu@denx.de6ca24c62006-04-21 18:30:47 +020072
73/*
74 * AT-PS/2 Multiplexer
75 */
76#ifdef CONFIG_BC3450_PS2
77# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
78# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
79# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020081# define CONFIG_BOARD_EARLY_INIT_R
82#endif /* CONFIG_BC3450_PS2 */
83
84/*
85 * PCI Mapping:
86 * 0x40000000 - 0x4fffffff - PCI Memory
87 * 0x50000000 - 0x50ffffff - PCI IO Space
88 */
89# define CONFIG_PCI 1
90# define CONFIG_PCI_PNP 1
Wolfgang Denk610cf362006-05-03 01:24:04 +020091/* #define CONFIG_PCI_SCAN_SHOW 1 */
TsiChung Liewf33fca22008-03-30 01:19:06 -050092#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +020093
94#define CONFIG_PCI_MEM_BUS 0x40000000
95#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
96#define CONFIG_PCI_MEM_SIZE 0x10000000
97
98#define CONFIG_PCI_IO_BUS 0x50000000
99#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
100#define CONFIG_PCI_IO_SIZE 0x01000000
101
102#define CONFIG_NET_MULTI 1
103/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200105#define CONFIG_NS8382X 1
106
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200107/*
108 * Video console
109 */
110# define CONFIG_VIDEO
111# define CONFIG_VIDEO_SM501
112# define CONFIG_VIDEO_SM501_32BPP
113# define CONFIG_CFB_CONSOLE
114# define CONFIG_VIDEO_LOGO
115# define CONFIG_VGA_AS_SINGLE_DEVICE
116# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
117# define CONFIG_VIDEO_SW_CURSOR
118# define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119# define CONFIG_SYS_CONSOLE_IS_IN_ENV
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200120
Wolfgang Denk610cf362006-05-03 01:24:04 +0200121/*
122 * Partitions
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200123 */
124#define CONFIG_MAC_PARTITION
125#define CONFIG_DOS_PARTITION
126#define CONFIG_ISO_PARTITION
127
Wolfgang Denk610cf362006-05-03 01:24:04 +0200128/*
129 * USB
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200130 */
131#ifdef CONFIG_BC3450_USB
132# define CONFIG_USB_OHCI
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200133# define CONFIG_USB_STORAGE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200134#endif /* CONFIG_BC3450_USB */
135
Wolfgang Denk610cf362006-05-03 01:24:04 +0200136/*
137 * POST support
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
140 CONFIG_SYS_POST_CPU | \
141 CONFIG_SYS_POST_I2C)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200142
143#ifdef CONFIG_POST
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200144/* preserve space for the post_word at end of on-chip SRAM */
145# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200146#endif /* CONFIG_POST */
147
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500148
Wolfgang Denk610cf362006-05-03 01:24:04 +0200149/*
Jon Loeliger11799432007-07-10 09:02:57 -0500150 * BOOTP options
151 */
152#define CONFIG_BOOTP_BOOTFILESIZE
153#define CONFIG_BOOTP_BOOTPATH
154#define CONFIG_BOOTP_GATEWAY
155#define CONFIG_BOOTP_HOSTNAME
156
157
158/*
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500159 * Command line configuration.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200160 */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500161#include <config_cmd_default.h>
162
163#define CONFIG_CMD_ASKENV
164#define CONFIG_CMD_DATE
165#define CONFIG_CMD_DHCP
166#define CONFIG_CMD_ECHO
167#define CONFIG_CMD_EEPROM
168#define CONFIG_CMD_I2C
169#define CONFIG_CMD_JFFS2
170#define CONFIG_CMD_MII
171#define CONFIG_CMD_NFS
172#define CONFIG_CMD_PING
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500173#define CONFIG_CMD_REGINFO
174#define CONFIG_CMD_SNTP
175#define CONFIG_CMD_BSP
176
177#ifdef CONFIG_VIDEO
178 #define CONFIG_CMD_BMP
179#endif
180
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200181#ifdef CONFIG_BC3450_IDE
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500182 #define CONFIG_CMD_IDE
183#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200184
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500185#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
186 #ifdef CONFIG_FAT
187 #define CONFIG_CMD_FAT
188 #endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200189
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500190 #ifdef CONFIG_EXT2
191 #define CONFIG_CMD_EXT2
192 #endif
193#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200194
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500195#ifdef CONFIG_BC3450_USB
196 #define CONFIG_CMD_USB
197#endif
Wolfgang Denk5728be32007-08-06 01:01:49 +0200198
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500199#ifdef CONFIG_PCI
200 #define CONFIG_CMD_PCI
201#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200202
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500203#ifdef CONFIG_POST
204 #define CONFIG_CMD_DIAG
205#endif
206
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200207
Wolfgang Denk610cf362006-05-03 01:24:04 +0200208#define CONFIG_TIMESTAMP /* display image timestamps */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200209
210#if (TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211# define CONFIG_SYS_LOWBOOT 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200212#endif
213
214/*
215 * Autobooting
216 */
217#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
218#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
219
220#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100221 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200222 "echo;"
223
224#undef CONFIG_BOOTARGS
225
226#define CONFIG_EXTRA_ENV_SETTINGS \
227 "netdev=eth0\0" \
228 "ipaddr=192.168.1.10\0" \
229 "serverip=192.168.1.3\0" \
230 "netmask=255.255.255.0\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200231 "hostname=bc3450\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200232 "rootpath=/opt/eldk/ppc_6xx\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200233 "kernel_addr=fc0a0000\0" \
234 "ramdisk_addr=fc1c0000\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200235 "ramargs=setenv bootargs root=/dev/ram rw\0" \
236 "nfsargs=setenv bootargs root=/dev/nfs rw " \
237 "nfsroot=$(serverip):$(rootpath)\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200238 "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200239 "addip=setenv bootargs $(bootargs) " \
240 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
241 ":$(hostname):$(netdev):off panic=1\0" \
242 "addcons=setenv bootargs $(bootargs) " \
243 "console=ttyS0,$(baudrate) console=tty0\0" \
244 "flash_self=run ramargs addip addcons;" \
245 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
246 "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
247 "net_nfs=tftp 200000 $(bootfile); " \
248 "run nfsargs addip addcons; bootm\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200249 "ide_nfs=run nfsargs addip addcons; " \
250 "disk 200000 0:1; bootm\0" \
251 "ide_ide=run ideargs addip addcons; " \
252 "disk 200000 0:1; bootm\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200253 "usb_self=run usbload; run ramargs addip addcons; " \
254 "bootm 200000 400000\0" \
255 "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
256 "usbboot 400000 0:2\0" \
257 "bootfile=uImage\0" \
258 "load=tftp 200000 $(u-boot)\0" \
259 "u-boot=u-boot.bin\0" \
260 "update=protect off FC000000 FC05FFFF;" \
261 "erase FC000000 FC05FFFF;" \
262 "cp.b 200000 FC000000 $(filesize);" \
263 "protect on FC000000 FC05FFFF\0" \
264 ""
265
266#define CONFIG_BOOTCOMMAND "run flash_self"
267
268/*
269 * IPB Bus clocking configuration.
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200272
273/*
274 * PCI Bus clocking configuration
275 *
276 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200278 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
281# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200282#endif
283
284/*
285 * I2C configuration
286 */
287#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200289
290/*
291 * I2C clock frequency
292 *
293 * Please notice, that the resulting clock frequency could differ from the
294 * configured value. This is because the I2C clock is derived from system
295 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200297 * approximation allways lies below the configured value, never above.
298 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
300#define CONFIG_SYS_I2C_SLAVE 0x7F
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200301
302/*
Wolfgang Denk610cf362006-05-03 01:24:04 +0200303 * EEPROM configuration for I²C EEPROM M24C32
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200304 * M24C64 should work also. For other EEPROMs config should be verified.
Wolfgang Denk610cf362006-05-03 01:24:04 +0200305 *
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200306 * The TQM5200 module may hold an EEPROM at address 0x50.
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
309#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
310#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
311#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200312
313/*
314 * RTC configuration
315 */
316#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
317# define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318# define CONFIG_SYS_I2C_RTC_ADDR 0x68
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200319#else
320# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
321# define CONFIG_BOARD_EARLY_INIT_R
322#endif
323
324/*
325 * Flash configuration
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200328
329/* use CFI flash driver if no module variant is spezified */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200331#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
333#define CONFIG_SYS_FLASH_EMPTY_INFO
334#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
335#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
336#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#if !defined(CONFIG_SYS_LOWBOOT)
339#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
340#else /* CONFIG_SYS_LOWBOOT */
341#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
342#endif /* CONFIG_SYS_LOWBOOT */
343#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200344 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
346#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200347
348/* Dynamic MTD partition support */
349#define CONFIG_JFFS2_CMDLINE
350#define MTDIDS_DEFAULT "nor0=TQM5200-0"
351#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
352 "1408k(kernel)," \
353 "2m(initrd)," \
354 "4m(small-fs)," \
355 "16m(big-fs)," \
356 "8m(misc)"
357
358/*
359 * Environment settings
360 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200361#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200362#define CONFIG_ENV_SIZE 0x10000
363#define CONFIG_ENV_SECT_SIZE 0x20000
364#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
365#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200366
367/*
368 * Memory map
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_MBAR 0xF0000000
371#define CONFIG_SYS_SDRAM_BASE 0x00000000
372#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200373
374/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200376#ifdef CONFIG_POST
377/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378# define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200379#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380# define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200381#endif /*CONFIG_POST*/
382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Bytes reserved for initial data */
384#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
385#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200386
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
388#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
389# define CONFIG_SYS_RAMBOOT 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200390#endif
391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
393#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
394#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200395
396/*
397 * Ethernet configuration
398 *
399 * Define CONFIG_FEC10MBIT to force FEC at 10MBIT
400 */
401#define CONFIG_MPC5xxx_FEC 1
402#undef CONFIG_FEC_10MBIT
403#define CONFIG_PHY_ADDR 0x00
404
405/*
406 * GPIO configuration on BC3450
407 *
Wolfgang Denk610cf362006-05-03 01:24:04 +0200408 * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
409 * PSC2: UART2 [0x xxxxxx4x]
410 * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
411 * PSC3: USB2 [0x xxxxx1xx]
412 * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
413 * (this has to match
414 * CONFIG_USB_CONFIG which is
415 * used by usb_ohci.c to set
416 * the USB ports)
417 * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
418 * (this is reset to '5'
419 * in FEC driver: fec.c)
420 * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
421 * ATA/CS: ??? [0x x1xxxxxx]
422 * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200423 * CS1: Use Pin gpio_wkup_6 as second
Wolfgang Denk610cf362006-05-03 01:24:04 +0200424 * SDRAM chip select (mem_cs1)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200425 * Timer: CAN2 / SPI
Wolfgang Denk610cf362006-05-03 01:24:04 +0200426 * I2C: CAN1 / I²C2 [0x bxxxxxxx]
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200427 */
428#ifdef CONFIG_BC3450_AC97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200430#else /* PSC2=UART2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200432#endif
433
434/*
435 * Miscellaneous configurable options
436 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_LONGHELP /* undef to save memory */
438#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500439#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200441#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200443#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
445#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
446#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200447
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200449 /* more extensive mem test */
450
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
452#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200453
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200455
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500459#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500461#endif
462
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200463/*
Jon Loeliger11799432007-07-10 09:02:57 -0500464 * Enable loopw command.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200465 */
466#define CONFIG_LOOPW
467
468/*
469 * Various low-level settings
470 */
471#if defined(CONFIG_MPC5200)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472# define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
473# define CONFIG_SYS_HID0_FINAL HID0_ICE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200474#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475# define CONFIG_SYS_HID0_INIT 0
476# define CONFIG_SYS_HID0_FINAL 0
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200477#endif
478
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
480#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
481#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
482# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200483#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200485#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
487#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200488
489/* automatic configuration of chip selects */
490#ifdef CONFIG_TQM5200
491# define CONFIG_LAST_STAGE_INIT
492#endif /* CONFIG_TQM5200 */
493
494/*
495 * SRAM - Do not map below 2 GB in address space, because this area is used
496 * for SDRAM autosizing.
497 */
498#ifdef CONFIG_TQM5200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499# define CONFIG_SYS_CS2_START 0xE5000000
500# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
501# define CONFIG_SYS_CS2_CFG 0x0004D930
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200502#endif /* CONFIG_TQM5200 */
503
504/*
505 * Grafic controller - Do not map below 2 GB in address space, because this
506 * area is used for SDRAM autosizing.
507 */
508#ifdef CONFIG_TQM5200
509# define SM501_FB_BASE 0xE0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
511# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
512# define CONFIG_SYS_CS1_CFG 0x8F48FF70
513# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200514#endif /* CONFIG_TQM5200 */
515
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_CS_BURST 0x00000000
517#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200518 /* flash and SM501 */
519
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_RESET_ADDRESS 0xff000000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200521
522/*
523 * USB stuff
524 */
525#define CONFIG_USB_CLOCK 0x0001BBBB
Wolfgang Denk610cf362006-05-03 01:24:04 +0200526#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200527
528/*
529 * IDE/ATA stuff Supports IDE harddisk
530 */
531#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
532
Wolfgang Denk610cf362006-05-03 01:24:04 +0200533#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
534#undef CONFIG_IDE_LED /* LED for ide not supported */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200535
Wolfgang Denk610cf362006-05-03 01:24:04 +0200536#define CONFIG_IDE_RESET /* reset for ide supported */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200537#define CONFIG_IDE_PREINIT
538
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200539#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
540#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200541
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200543
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200545
546/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200548
549/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200550#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200551
552/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200554
555/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200556#define CONFIG_SYS_ATA_STRIDE 4
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200557
558#endif /* __CONFIG_H */