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wdenkc1896002003-12-28 11:44:59 +00001/*
2 * (C) Copyright 2003
wdenkd4ca31c2004-01-02 14:00:00 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
6 *
7 * TOP5200 differences from IceCube:
8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
10 * 1 SDRAM/DDRAM Bank up to 256 MB
11 * local VPD I2C Bus is software driven and uses
12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
13 * FLASH is re-located at 0xff000000
14 * Internal regs are at 0xf0000000
wdenkc1896002003-12-28 11:44:59 +000015 * Reset jumps to 0x00000100
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
wdenkcbd8a352004-02-24 02:00:03 +000044#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkc1896002003-12-28 11:44:59 +000045#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */
46#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */
47
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenkc1896002003-12-28 11:44:59 +000049
50#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51#define BOOTFLAG_WARM 0x02 /* Software reboot */
52
Becky Bruce31d82672008-05-08 19:02:12 -050053#define CONFIG_HIGH_BATS 1 /* High BATs supported */
54
wdenkc1896002003-12-28 11:44:59 +000055/*
56 * Serial console configuration
57 */
58#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
59#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkc1896002003-12-28 11:44:59 +000061
62
wdenk4d13cba2004-03-14 14:09:05 +000063#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenkc1896002003-12-28 11:44:59 +000064/*
65 * PCI Mapping:
66 * 0x40000000 - 0x4fffffff - PCI Memory
67 * 0x50000000 - 0x50ffffff - PCI IO Space
68 */
69# define CONFIG_PCI 1
70# define CONFIG_PCI_PNP 1
71# define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -050072# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
wdenkc1896002003-12-28 11:44:59 +000073
74# define CONFIG_PCI_MEM_BUS 0x40000000
75# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
76# define CONFIG_PCI_MEM_SIZE 0x10000000
77
78# define CONFIG_PCI_IO_BUS 0x50000000
79# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
80# define CONFIG_PCI_IO_SIZE 0x01000000
81
wdenkc1896002003-12-28 11:44:59 +000082#endif
83
wdenk4d13cba2004-03-14 14:09:05 +000084/* USB */
85#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
86
87# define CONFIG_USB_OHCI
88# define CONFIG_USB_CLOCK 0x0001bbbb
wdenk498b8db2004-04-18 22:26:17 +000089# if defined (CONFIG_EVAL5200)
90# define CONFIG_USB_CONFIG 0x00005100
91# else
92# define CONFIG_USB_CONFIG 0x00001000
93# endif
wdenk4d13cba2004-03-14 14:09:05 +000094# define CONFIG_DOS_PARTITION
95# define CONFIG_USB_STORAGE
96
wdenk4d13cba2004-03-14 14:09:05 +000097#endif
98
99/* IDE */
100#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
wdenk4d13cba2004-03-14 14:09:05 +0000101# define CONFIG_DOS_PARTITION
wdenk4d13cba2004-03-14 14:09:05 +0000102#endif
103
wdenkc1896002003-12-28 11:44:59 +0000104
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500105/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500106 * BOOTP options
107 */
108#define CONFIG_BOOTP_BOOTFILESIZE
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_GATEWAY
111#define CONFIG_BOOTP_HOSTNAME
112
113
114/*
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500115 * Command line configuration.
116 */
117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_ASKENV
120#define CONFIG_CMD_BEDBUG
121#define CONFIG_CMD_DATE
122#define CONFIG_CMD_DHCP
123#define CONFIG_CMD_EEPROM
124#define CONFIG_CMD_ELF
125#define CONFIG_CMD_I2C
126#define CONFIG_CMD_IMMAP
127#define CONFIG_CMD_MII
128#define CONFIG_CMD_REGINFO
129
130#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200)
131#define CONFIG_CMD_FAT
132#define CONFIG_CMD_IDE
133#define CONFIG_CMD_USB
134#define CONFIG_CMD_PCI
135#endif
136
wdenkc1896002003-12-28 11:44:59 +0000137
138/*
wdenk4d13cba2004-03-14 14:09:05 +0000139 * MUST be low boot - HIGHBOOT is not supported anymore
wdenkd4ca31c2004-01-02 14:00:00 +0000140 */
141#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142# define CONFIG_SYS_LOWBOOT 1
143# define CONFIG_SYS_LOWBOOT16 1
wdenk4d13cba2004-03-14 14:09:05 +0000144#else
145# error "TEXT_BASE must be 0xff000000"
wdenkd4ca31c2004-01-02 14:00:00 +0000146#endif
147
148/*
wdenkc1896002003-12-28 11:44:59 +0000149 * Autobooting
150 */
151#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkd4ca31c2004-01-02 14:00:00 +0000152
153#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100154 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd4ca31c2004-01-02 14:00:00 +0000155 "echo"
156
157#undef CONFIG_BOOTARGS
158
159#define CONFIG_EXTRA_ENV_SETTINGS \
160 "netdev=eth0\0" \
161 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100162 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000163 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100164 "addip=setenv bootargs ${bootargs} " \
165 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
166 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000167 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100168 "bootm ${kernel_addr}\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000169 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100170 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
171 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000172 "rootpath=/opt/eldk/ppc_82xx\0" \
173 "bootfile=/tftpboot/MPC5200/uImage\0" \
174 ""
175
176#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc1896002003-12-28 11:44:59 +0000177
178/*
179 * IPB Bus clocking configuration.
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkd4ca31c2004-01-02 14:00:00 +0000182
wdenkc1896002003-12-28 11:44:59 +0000183/*
184 * I2C configuration
185 */
186/*
187 * EEPROM configuration
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
190#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
wdenkc1896002003-12-28 11:44:59 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
193#define CONFIG_SYS_EEPROM_SIZE 0x2000
wdenkd4ca31c2004-01-02 14:00:00 +0000194
wdenkc1896002003-12-28 11:44:59 +0000195#define CONFIG_ENV_OVERWRITE
196#define CONFIG_MISC_INIT_R
wdenkd4ca31c2004-01-02 14:00:00 +0000197
wdenkc1896002003-12-28 11:44:59 +0000198#undef CONFIG_HARD_I2C /* I2C with hardware support */
wdenk4d13cba2004-03-14 14:09:05 +0000199#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */
wdenkd4ca31c2004-01-02 14:00:00 +0000200
wdenkc1896002003-12-28 11:44:59 +0000201#if defined (CONFIG_SOFT_I2C)
202# define SDA0 0x40
203# define SCL0 0x80
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00))
205# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08))
206# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c))
207# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20))
208# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04))
wdenkc1896002003-12-28 11:44:59 +0000209# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
210# define I2C_READ ((DVI0&SDA0)?1:0)
211# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
212# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;}
213# define I2C_DELAY {udelay(5);}
214# define I2C_ACTIVE {DDR0|=SDA0;}
215# define I2C_TRISTATE {DDR0&=~SDA0;}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216# define CONFIG_SYS_I2C_SPEED 100000
217# define CONFIG_SYS_I2C_SLAVE 0x7F
218#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
219#define CONFIG_SYS_I2C_FACT_ADDR 0x57
wdenkc1896002003-12-28 11:44:59 +0000220#endif
wdenkd4ca31c2004-01-02 14:00:00 +0000221
222#if defined (CONFIG_HARD_I2C)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
224# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
225# define CONFIG_SYS_I2C_SLAVE 0x7F
226#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
227#define CONFIG_SYS_I2C_FACT_ADDR 0x54
wdenkd4ca31c2004-01-02 14:00:00 +0000228#endif
wdenkc1896002003-12-28 11:44:59 +0000229
230/*
231 * Flash configuration, expect one 16 Megabyte Bank at most
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_FLASH_BASE 0xff000000
234#define CONFIG_SYS_FLASH_SIZE 0x01000000
235#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
236#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0)
wdenkc1896002003-12-28 11:44:59 +0000237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenkc1896002003-12-28 11:44:59 +0000239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
241#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenkc1896002003-12-28 11:44:59 +0000242
243#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
244
wdenkd4ca31c2004-01-02 14:00:00 +0000245/*
246 * DRAM configuration - will be read from VPD later... TODO!
247 */
248#if 0
249/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_DRAM_DDR 0
251#define CONFIG_SYS_DRAM_EMODE 0
252#define CONFIG_SYS_DRAM_MODE 0x008D
253#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
254#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00
255#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004
256#define CONFIG_SYS_DRAM_TAP_DEL 0x08
257#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
wdenkd4ca31c2004-01-02 14:00:00 +0000258#endif
259#if 1
260/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_DRAM_DDR 0
262#define CONFIG_SYS_DRAM_EMODE 0
263#define CONFIG_SYS_DRAM_MODE 0x00CD
264#define CONFIG_SYS_DRAM_CONTROL 0x514F0000
265#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00
266#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004
267#define CONFIG_SYS_DRAM_TAP_DEL 0x08
268#define CONFIG_SYS_DRAM_RAM_SIZE 0x19
wdenkd4ca31c2004-01-02 14:00:00 +0000269#endif
270
wdenkc1896002003-12-28 11:44:59 +0000271/*
272 * Environment settings
273 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200274#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200275#define CONFIG_ENV_OFFSET 0x1000
276#define CONFIG_ENV_SIZE 0x0700
wdenkc1896002003-12-28 11:44:59 +0000277
wdenkd4ca31c2004-01-02 14:00:00 +0000278/*
279 * VPD settings
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_FACT_OFFSET 0x1800
282#define CONFIG_SYS_FACT_SIZE 0x0800
wdenkd4ca31c2004-01-02 14:00:00 +0000283
wdenkc1896002003-12-28 11:44:59 +0000284/*
wdenkd4ca31c2004-01-02 14:00:00 +0000285 * Memory map
286 *
287 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
wdenkc1896002003-12-28 11:44:59 +0000288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
290#define CONFIG_SYS_SDRAM_BASE 0x00000000
291#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
wdenkc1896002003-12-28 11:44:59 +0000292
293/* Use SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
295#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
wdenkc1896002003-12-28 11:44:59 +0000296
297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
299#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
300#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc1896002003-12-28 11:44:59 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
303#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
304# define CONFIG_SYS_RAMBOOT 1
wdenkc1896002003-12-28 11:44:59 +0000305#endif
306
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
308#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
309#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc1896002003-12-28 11:44:59 +0000310
311/*
312 * Ethernet configuration
313 */
wdenkcbd8a352004-02-24 02:00:03 +0000314#define CONFIG_MPC5xxx_FEC 1
wdenkc1896002003-12-28 11:44:59 +0000315#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
wdenkd4ca31c2004-01-02 14:00:00 +0000316#define CONFIG_PHY_ADDR 0x1f
wdenkc1896002003-12-28 11:44:59 +0000317#define CONFIG_PHY_TYPE 0x79c874
318/*
wdenkd4ca31c2004-01-02 14:00:00 +0000319 * GPIO configuration:
320 * PSC1,2,3 predefined as UART
321 * PCI disabled
wdenkc1896002003-12-28 11:44:59 +0000322 * Ethernet 100 with MD
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044
wdenkc1896002003-12-28 11:44:59 +0000325
326/*
327 * Miscellaneous configurable options
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_LONGHELP /* undef to save memory */
330#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500331#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000333#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000335#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
337#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
338#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc1896002003-12-28 11:44:59 +0000339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
341#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
wdenkc1896002003-12-28 11:44:59 +0000342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
wdenkc1896002003-12-28 11:44:59 +0000344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc1896002003-12-28 11:44:59 +0000346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500348#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerd794cfe2007-07-04 22:31:15 -0500350#endif
351
352
wdenk63e73c92004-02-23 22:22:28 +0000353#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */
354 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */
355 #define RTC(reg) (0xf0010000+reg)
356 /* setup CS2 for M48T08. Must MAP 64kB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357 #define CONFIG_SYS_CS2_START RTC(0)
358 #define CONFIG_SYS_CS2_SIZE 0x10000
wdenk63e73c92004-02-23 22:22:28 +0000359 /* setup CS2 configuration register: */
360 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */
361 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362 #define CONFIG_SYS_CS2_CFG 0x00047800
wdenk63e73c92004-02-23 22:22:28 +0000363#else
364 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
365#endif
wdenk1c437712004-01-16 00:30:56 +0000366
wdenkc1896002003-12-28 11:44:59 +0000367/*
368 * Various low-level settings
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
371#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenkc1896002003-12-28 11:44:59 +0000372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
374#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
375#define CONFIG_SYS_BOOTCS_CFG 0x00047801
376#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
377#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenkc1896002003-12-28 11:44:59 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_CS_BURST 0x00000000
380#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenkc1896002003-12-28 11:44:59 +0000381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
wdenkc1896002003-12-28 11:44:59 +0000383
wdenk4d13cba2004-03-14 14:09:05 +0000384/*-----------------------------------------------------------------------
385 * IDE/ATA stuff Supports IDE harddisk
386 *-----------------------------------------------------------------------
387 */
388
389#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
390
391#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
392#undef CONFIG_IDE_LED /* LED for ide not supported */
393
394#define CONFIG_IDE_RESET 1
395#define CONFIG_IDE_PREINIT
396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
398#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk4d13cba2004-03-14 14:09:05 +0000399
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk4d13cba2004-03-14 14:09:05 +0000401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
wdenk4d13cba2004-03-14 14:09:05 +0000403
404/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
wdenk4d13cba2004-03-14 14:09:05 +0000406
407/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
wdenk4d13cba2004-03-14 14:09:05 +0000409
410/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c)
wdenk4d13cba2004-03-14 14:09:05 +0000412
413/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_ATA_STRIDE 4
wdenk4d13cba2004-03-14 14:09:05 +0000415
wdenkc1896002003-12-28 11:44:59 +0000416#endif /* __CONFIG_H */