blob: bcf37d911c230d884a2d12ab359285e9b0a0b461 [file] [log] [blame]
wdenk71f95112003-06-15 22:40:42 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenk71f95112003-06-15 22:40:42 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1
37#define CONFIG_MPC860T 1
38#define CONFIG_MPC862 1
39
40#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
41
42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43#undef CONFIG_8xx_CONS_SMC2
44#undef CONFIG_8xx_CONS_NONE
45
46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
47
wdenkae3af052003-08-07 22:18:11 +000048#define CONFIG_BOOTCOUNT_LIMIT
wdenk71f95112003-06-15 22:40:42 +000049
wdenkae3af052003-08-07 22:18:11 +000050#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk71f95112003-06-15 22:40:42 +000051
52#define CONFIG_BOARD_TYPES 1 /* support board types */
53
54#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010055 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk71f95112003-06-15 22:40:42 +000056 "echo"
57
58#undef CONFIG_BOOTARGS
59
60#define CONFIG_EXTRA_ENV_SETTINGS \
61 "netdev=eth0\0" \
62 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "nfsroot=${serverip}:${rootpath}\0" \
wdenk71f95112003-06-15 22:40:42 +000064 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010065 "addip=setenv bootargs ${bootargs} " \
66 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
67 ":${hostname}:${netdev}:off panic=1\0" \
wdenk71f95112003-06-15 22:40:42 +000068 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "bootm ${kernel_addr}\0" \
wdenk71f95112003-06-15 22:40:42 +000070 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
72 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk71f95112003-06-15 22:40:42 +000073 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020074 "hostname=TQM862M\0" \
75 "bootfile=TQM862M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020076 "fdt_addr=40080000\0" \
77 "kernel_addr=400A0000\0" \
78 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020079 "u-boot=TQM862M/u-image.bin\0" \
80 "load=tftp 200000 ${u-boot}\0" \
81 "update=prot off 40000000 +${filesize};" \
82 "era 40000000 +${filesize};" \
83 "cp.b 200000 40000000 ${filesize};" \
84 "sete filesize;save\0" \
wdenk71f95112003-06-15 22:40:42 +000085 ""
86#define CONFIG_BOOTCOMMAND "run flash_self"
87
88#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk71f95112003-06-15 22:40:42 +000090
91#undef CONFIG_WATCHDOG /* watchdog disabled */
92
93#define CONFIG_STATUS_LED 1 /* Status LED enabled */
94
95#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
96
Jon Loeliger37d4bb72007-07-09 21:38:02 -050097/*
98 * BOOTP options
99 */
100#define CONFIG_BOOTP_SUBNETMASK
101#define CONFIG_BOOTP_GATEWAY
102#define CONFIG_BOOTP_HOSTNAME
103#define CONFIG_BOOTP_BOOTPATH
104#define CONFIG_BOOTP_BOOTFILESIZE
105
wdenk71f95112003-06-15 22:40:42 +0000106
107#define CONFIG_MAC_PARTITION
108#define CONFIG_DOS_PARTITION
109
110#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
111
wdenk71f95112003-06-15 22:40:42 +0000112
Jon Loeliger26946902007-07-04 22:30:50 -0500113/*
114 * Command line configuration.
115 */
116#include <config_cmd_default.h>
117
118#define CONFIG_CMD_ASKENV
119#define CONFIG_CMD_DATE
120#define CONFIG_CMD_DHCP
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200121#define CONFIG_CMD_ELF
Jon Loeliger26946902007-07-04 22:30:50 -0500122#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200123#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500124#define CONFIG_CMD_NFS
125#define CONFIG_CMD_SNTP
126
wdenk71f95112003-06-15 22:40:42 +0000127
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200128#define CONFIG_NETCONSOLE
129
130
wdenk71f95112003-06-15 22:40:42 +0000131/*
132 * Miscellaneous configurable options
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_LONGHELP /* undef to save memory */
135#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +0000136
Wolfgang Denk2751a952006-10-28 02:29:14 +0200137#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
139#ifdef CONFIG_SYS_HUSH_PARSER
140#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk71f95112003-06-15 22:40:42 +0000141#endif
142
Jon Loeliger26946902007-07-04 22:30:50 -0500143#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000145#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000147#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
149#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
150#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk71f95112003-06-15 22:40:42 +0000151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
153#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk71f95112003-06-15 22:40:42 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk71f95112003-06-15 22:40:42 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk71f95112003-06-15 22:40:42 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk71f95112003-06-15 22:40:42 +0000160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 */
166/*-----------------------------------------------------------------------
167 * Internal Memory Mapped Register
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_IMMR 0xFFF00000
wdenk71f95112003-06-15 22:40:42 +0000170
171/*-----------------------------------------------------------------------
172 * Definitions for initial stack pointer and data area (in DPRAM)
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
175#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
176#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
177#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
178#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk71f95112003-06-15 22:40:42 +0000179
180/*-----------------------------------------------------------------------
181 * Start addresses for the final memory configuration
182 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk71f95112003-06-15 22:40:42 +0000184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_SDRAM_BASE 0x00000000
186#define CONFIG_SYS_FLASH_BASE 0x40000000
187#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
188#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
189#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk71f95112003-06-15 22:40:42 +0000190
191/*
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization.
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk71f95112003-06-15 22:40:42 +0000197
198/*-----------------------------------------------------------------------
199 * FLASH organization
200 */
wdenk71f95112003-06-15 22:40:42 +0000201
Martin Krausee318d9e2007-09-27 11:10:08 +0200202/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200204#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
206#define CONFIG_SYS_FLASH_EMPTY_INFO
207#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
208#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
209#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk71f95112003-06-15 22:40:42 +0000210
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200211#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
213#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
214#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenk71f95112003-06-15 22:40:42 +0000215
216/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200217#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
218#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk71f95112003-06-15 22:40:42 +0000219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200221
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200222#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
223
wdenk71f95112003-06-15 22:40:42 +0000224/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200225 * Dynamic MTD partition support
226 */
227#define CONFIG_JFFS2_CMDLINE
228#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
229
230#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
231 "128k(dtb)," \
232 "1920k(kernel)," \
233 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200234 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200235
236/*-----------------------------------------------------------------------
wdenk71f95112003-06-15 22:40:42 +0000237 * Hardware Information Block
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
240#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
241#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenk71f95112003-06-15 22:40:42 +0000242
243/*-----------------------------------------------------------------------
244 * Cache Configuration
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500247#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk71f95112003-06-15 22:40:42 +0000249#endif
250
251/*-----------------------------------------------------------------------
252 * SYPCR - System Protection Control 11-9
253 * SYPCR can only be written once after reset!
254 *-----------------------------------------------------------------------
255 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
256 */
257#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk71f95112003-06-15 22:40:42 +0000259 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
260#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk71f95112003-06-15 22:40:42 +0000262#endif
263
264/*-----------------------------------------------------------------------
265 * SIUMCR - SIU Module Configuration 11-6
266 *-----------------------------------------------------------------------
267 * PCMCIA config., multi-function pin tri-state
268 */
269#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk71f95112003-06-15 22:40:42 +0000271#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk71f95112003-06-15 22:40:42 +0000273#endif /* CONFIG_CAN_DRIVER */
274
275/*-----------------------------------------------------------------------
276 * TBSCR - Time Base Status and Control 11-26
277 *-----------------------------------------------------------------------
278 * Clear Reference Interrupt Status, Timebase freezing enabled
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenk71f95112003-06-15 22:40:42 +0000281
282/*-----------------------------------------------------------------------
283 * RTCSC - Real-Time Clock Status and Control Register 11-27
284 *-----------------------------------------------------------------------
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenk71f95112003-06-15 22:40:42 +0000287
288/*-----------------------------------------------------------------------
289 * PISCR - Periodic Interrupt Status and Control 11-31
290 *-----------------------------------------------------------------------
291 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk71f95112003-06-15 22:40:42 +0000294
295/*-----------------------------------------------------------------------
296 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
297 *-----------------------------------------------------------------------
298 * Reset PLL lock status sticky bit, timer expired status bit and timer
299 * interrupt status bit
wdenk71f95112003-06-15 22:40:42 +0000300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenk71f95112003-06-15 22:40:42 +0000302
303/*-----------------------------------------------------------------------
304 * SCCR - System Clock and reset Control Register 15-27
305 *-----------------------------------------------------------------------
306 * Set clock output, timebase and RTC source and divider,
307 * power management and some other internal clocks
308 */
309#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenk71f95112003-06-15 22:40:42 +0000311 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
312 SCCR_DFALCD00)
wdenk71f95112003-06-15 22:40:42 +0000313
314/*-----------------------------------------------------------------------
315 * PCMCIA stuff
316 *-----------------------------------------------------------------------
317 *
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
320#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
321#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
322#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
323#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
324#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
325#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
326#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenk71f95112003-06-15 22:40:42 +0000327
328/*-----------------------------------------------------------------------
329 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
330 *-----------------------------------------------------------------------
331 */
332
333#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
334
335#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336#undef CONFIG_IDE_LED /* LED for ide not supported */
337#undef CONFIG_IDE_RESET /* reset for ide not supported */
338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
340#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk71f95112003-06-15 22:40:42 +0000341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk71f95112003-06-15 22:40:42 +0000343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenk71f95112003-06-15 22:40:42 +0000345
346/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk71f95112003-06-15 22:40:42 +0000348
349/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenk71f95112003-06-15 22:40:42 +0000351
352/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenk71f95112003-06-15 22:40:42 +0000354
355/*-----------------------------------------------------------------------
356 *
357 *-----------------------------------------------------------------------
358 *
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_DER 0
wdenk71f95112003-06-15 22:40:42 +0000361
362/*
363 * Init Memory Controller:
364 *
365 * BR0/1 and OR0/1 (FLASH)
366 */
367
368#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
369#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
370
371/* used to re-map FLASH both when starting from SRAM or FLASH:
372 * restrict access enough to keep SRAM working (if any)
373 * but not too much to meddle with FLASH accesses
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
376#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenk71f95112003-06-15 22:40:42 +0000377
378/*
379 * FLASH timing:
380 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk71f95112003-06-15 22:40:42 +0000382 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenk71f95112003-06-15 22:40:42 +0000383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
385#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
386#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000387
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
389#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
390#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000391
392/*
393 * BR2/3 and OR2/3 (SDRAM)
394 *
395 */
396#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
397#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
398#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
399
400/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenk71f95112003-06-15 22:40:42 +0000402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
404#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000405
406#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
408#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenk71f95112003-06-15 22:40:42 +0000409#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
411#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
412#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
413#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenk71f95112003-06-15 22:40:42 +0000414 BR_PS_8 | BR_MS_UPMB | BR_V )
415#endif /* CONFIG_CAN_DRIVER */
416
417/*
418 * Memory Periodic Timer Prescaler
419 *
420 * The Divider for PTA (refresh timer) configuration is based on an
421 * example SDRAM configuration (64 MBit, one bank). The adjustment to
422 * the number of chip selects (NCS) and the actually needed refresh
423 * rate is done by setting MPTPR.
424 *
425 * PTA is calculated from
426 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
427 *
428 * gclk CPU clock (not bus clock!)
429 * Trefresh Refresh cycle * 4 (four word bursts used)
430 *
431 * 4096 Rows from SDRAM example configuration
432 * 1000 factor s -> ms
433 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
434 * 4 Number of refresh cycles per period
435 * 64 Refresh cycle in ms per number of rows
436 * --------------------------------------------
437 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
438 *
439 * 50 MHz => 50.000.000 / Divider = 98
440 * 66 Mhz => 66.000.000 / Divider = 129
441 * 80 Mhz => 80.000.000 / Divider = 156
442 * 100 Mhz => 100.000.000 / Divider = 195
443 */
wdenke9132ea2004-04-24 23:23:30 +0000444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
446#define CONFIG_SYS_MAMR_PTA 98
wdenk71f95112003-06-15 22:40:42 +0000447
448/*
449 * For 16 MBit, refresh rates could be 31.3 us
450 * (= 64 ms / 2K = 125 / quad bursts).
451 * For a simpler initialization, 15.6 us is used instead.
452 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
454 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenk71f95112003-06-15 22:40:42 +0000455 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
457#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk71f95112003-06-15 22:40:42 +0000458
459/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
461#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk71f95112003-06-15 22:40:42 +0000462
463/*
464 * MAMR settings for SDRAM
465 */
466
467/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk71f95112003-06-15 22:40:42 +0000469 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
470 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
471/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk71f95112003-06-15 22:40:42 +0000473 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
474 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
475
476
477/*
478 * Internal Definitions
479 *
480 * Boot Flags
481 */
482#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
483#define BOOTFLAG_WARM 0x02 /* Software reboot */
484
485#define CONFIG_NET_MULTI
486#define CONFIG_SCC1_ENET
487#define CONFIG_FEC_ENET
488#define CONFIG_ETHPRIME "SCC ETHERNET"
489
490#endif /* __CONFIG_H */