wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Marius Groeger <mgroeger@sysgo.de> |
| 5 | * |
| 6 | * (C) Copyright 2002 |
| 7 | * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> |
| 8 | * |
| 9 | * (C) Copyright 2003 |
| 10 | * Texas Instruments, <www.ti.com> |
| 11 | * Kshitij Gupta <Kshitij@ti.com> |
| 12 | * |
| 13 | * See file CREDITS for list of people who contributed to this |
| 14 | * project. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or |
| 17 | * modify it under the terms of the GNU General Public License as |
| 18 | * published by the Free Software Foundation; either version 2 of |
| 19 | * the License, or (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
| 27 | * along with this program; if not, write to the Free Software |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 29 | * MA 02111-1307 USA |
| 30 | */ |
| 31 | |
| 32 | #include <common.h> |
| 33 | #if defined(CONFIG_OMAP730) |
| 34 | #include <./configs/omap730.h> |
| 35 | #endif |
| 36 | |
| 37 | int test_boot_mode(void); |
| 38 | void spin_up_leds(void); |
| 39 | void flash__init (void); |
| 40 | void ether__init (void); |
| 41 | void set_muxconf_regs (void); |
| 42 | void peripheral_power_enable (void); |
| 43 | |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 44 | #define FLASH_ON_CS0 1 |
| 45 | #define FLASH_ON_CS3 0 |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 46 | |
| 47 | static inline void delay (unsigned long loops) |
| 48 | { |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 49 | __asm__ volatile ("1:\n" |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 50 | "subs %0, %1, #1\n" |
| 51 | "bne 1b":"=r" (loops):"0" (loops)); |
| 52 | } |
| 53 | |
| 54 | int test_boot_mode(void) |
| 55 | { |
| 56 | /* Check for CS0 and CS3 address decode swapping */ |
| 57 | if (*((volatile int *)EMIFS_CONFIG) & 0x00000002) |
| 58 | return(FLASH_ON_CS3); |
| 59 | else |
| 60 | return(FLASH_ON_CS0); |
| 61 | } |
| 62 | |
| 63 | /* Toggle backup LED indication */ |
| 64 | void toggle_backup_led(void) |
| 65 | { |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 66 | static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */ |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 67 | volatile unsigned int *IOConfReg; |
| 68 | |
| 69 | |
| 70 | IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT); |
| 71 | |
| 72 | if (backupLEDState != 0) { |
| 73 | *IOConfReg &= (0xFFFFEFFF); |
| 74 | backupLEDState = 0; |
| 75 | } else { |
| 76 | *IOConfReg |= (0x00001000); |
| 77 | backupLEDState = 1; |
| 78 | } |
| 79 | } |
| 80 | |
| 81 | /* |
| 82 | * Miscellaneous platform dependent initialisations |
| 83 | */ |
| 84 | |
| 85 | int board_init (void) |
| 86 | { |
| 87 | volatile unsigned int *IOConfReg; |
| 88 | |
| 89 | |
| 90 | DECLARE_GLOBAL_DATA_PTR; |
| 91 | |
| 92 | /* arch number of OMAP 730 P2 Board - Same as the Innovator! */ |
| 93 | gd->bd->bi_arch_number = 491; |
| 94 | |
| 95 | /* adress of boot parameters */ |
| 96 | gd->bd->bi_boot_params = 0x10000100; |
| 97 | |
| 98 | /* Configure MUX settings */ |
| 99 | set_muxconf_regs (); |
| 100 | |
| 101 | peripheral_power_enable (); |
| 102 | |
| 103 | |
| 104 | /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */ |
| 105 | toggle_backup_led(); |
| 106 | |
| 107 | /* Hold GSM in reset until needed */ |
| 108 | *((volatile unsigned short *)M_CTL) &= ~1; |
| 109 | |
| 110 | |
| 111 | /* |
| 112 | * CSx timings, GPIO Mux ... setup |
| 113 | */ |
| 114 | |
| 115 | /* Flash: CS0 timings setup */ |
| 116 | *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3; |
| 117 | *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088; |
| 118 | |
| 119 | /* Ethernet support trough the debug board */ |
| 120 | /* CS1 timings setup */ |
| 121 | *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3; |
| 122 | *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000; |
| 123 | |
| 124 | /* this speeds up your boot a quite a bit. However to make it |
| 125 | * work, you need make sure your kernel startup flush bug is fixed. |
| 126 | * ... rkw ... |
| 127 | */ |
| 128 | icache_enable (); |
| 129 | |
| 130 | flash__init (); |
| 131 | ether__init (); |
| 132 | |
| 133 | return 0; |
| 134 | } |
| 135 | |
| 136 | int misc_init_r (void) |
| 137 | { |
| 138 | /* currently empty */ |
| 139 | return (0); |
| 140 | } |
| 141 | |
| 142 | /****************************** |
| 143 | Routine: |
| 144 | Description: |
| 145 | ******************************/ |
| 146 | void flash__init (void) |
| 147 | { |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 148 | unsigned int regval; |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 149 | |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 150 | regval = *((volatile unsigned int *) EMIFS_CONFIG); |
| 151 | /* Turn off write protection for flash devices. */ |
| 152 | regval = regval | 0x0001; |
| 153 | *((volatile unsigned int *) EMIFS_CONFIG) = regval; |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | /************************************************************* |
| 157 | Routine:ether__init |
| 158 | Description: take the Ethernet controller out of reset and wait |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 159 | for the EEPROM load to complete. |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 160 | *************************************************************/ |
| 161 | void ether__init (void) |
| 162 | { |
| 163 | #define LAN_RESET_REGISTER 0x0400001c |
| 164 | |
| 165 | *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; |
| 166 | do { |
| 167 | *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; |
| 168 | udelay (100); |
| 169 | } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); |
| 170 | |
| 171 | do { |
| 172 | *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; |
| 173 | udelay (100); |
| 174 | } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); |
| 175 | |
| 176 | #define ETH_CONTROL_REG 0x0400030b |
| 177 | |
| 178 | *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; |
| 179 | udelay (100); |
| 180 | } |
| 181 | |
| 182 | /****************************** |
| 183 | Routine: |
| 184 | Description: |
| 185 | ******************************/ |
| 186 | int dram_init (void) |
| 187 | { |
| 188 | DECLARE_GLOBAL_DATA_PTR; |
| 189 | |
| 190 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 191 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
| 192 | |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | /****************************************************** |
| 197 | Routine: set_muxconf_regs |
| 198 | Description: Setting up the configuration Mux registers |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 199 | specific to the hardware |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 200 | *******************************************************/ |
| 201 | void set_muxconf_regs (void) |
| 202 | { |
| 203 | volatile unsigned int *MuxConfReg; |
| 204 | /* set each registers to its reset value; */ |
| 205 | |
| 206 | /* |
| 207 | * Backup LED Indication |
| 208 | */ |
| 209 | |
| 210 | /* Configure MUXed pin. Mode 6: GPIO_140 */ |
| 211 | MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10); |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 212 | *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */ |
| 213 | *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */ |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 214 | |
| 215 | /* Configure GPIO_140 as output */ |
| 216 | MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL); |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 217 | *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */ |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 218 | |
| 219 | /* |
| 220 | * Configure GPIOs for battery charge & feedback |
| 221 | */ |
| 222 | |
| 223 | /* Configure MUXed pin. Mode 6: GPIO_35 */ |
| 224 | MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 225 | *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */ |
| 226 | *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */ |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 227 | |
| 228 | /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */ |
| 229 | MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5); |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 230 | *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */ |
| 231 | *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */ |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 232 | |
| 233 | MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL); |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 234 | *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */ |
| 235 | *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */ |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 236 | |
| 237 | /* |
| 238 | * Allow battery charge |
| 239 | */ |
| 240 | |
| 241 | MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT); |
wdenk | 1eaeb58 | 2004-06-08 00:22:43 +0000 | [diff] [blame^] | 242 | *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */ |
wdenk | a56bd92 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 243 | |
| 244 | /* |
| 245 | * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, |
| 246 | * It is used as the Ethernet controller interrupt |
| 247 | */ |
| 248 | MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9); |
| 249 | *MuxConfReg &= 0x1FFFFFFF; |
| 250 | } |
| 251 | |
| 252 | /****************************************************** |
| 253 | Routine: peripheral_power_enable |
| 254 | Description: Enable the power for UART1 |
| 255 | *******************************************************/ |
| 256 | void peripheral_power_enable (void) |
| 257 | { |
| 258 | volatile unsigned int *MuxConfReg; |
| 259 | |
| 260 | |
| 261 | /* Set up pins used by UART */ |
| 262 | |
| 263 | /* Start UART clock (48MHz) */ |
| 264 | MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG); |
| 265 | *MuxConfReg &= (0xFFFFFFF7); |
| 266 | *MuxConfReg |= (0x00000008); |
| 267 | |
| 268 | /* Get the UART pin in mode0 */ |
| 269 | MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); |
| 270 | *MuxConfReg &= (0xFF1FFFFF); |
| 271 | *MuxConfReg &= (0xF1FFFFFF); |
| 272 | } |