Weijie Gao | 23f1716 | 2018-12-20 16:12:53 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2018 MediaTek Inc. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | * Author: Mark Lee <mark-mc.lee@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <dm.h> |
| 11 | #include <malloc.h> |
| 12 | #include <miiphy.h> |
| 13 | #include <regmap.h> |
| 14 | #include <reset.h> |
| 15 | #include <syscon.h> |
| 16 | #include <wait_bit.h> |
| 17 | #include <asm/gpio.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <linux/err.h> |
| 20 | #include <linux/ioport.h> |
| 21 | #include <linux/mdio.h> |
| 22 | #include <linux/mii.h> |
| 23 | |
| 24 | #include "mtk_eth.h" |
| 25 | |
| 26 | #define NUM_TX_DESC 24 |
| 27 | #define NUM_RX_DESC 24 |
| 28 | #define TX_TOTAL_BUF_SIZE (NUM_TX_DESC * PKTSIZE_ALIGN) |
| 29 | #define RX_TOTAL_BUF_SIZE (NUM_RX_DESC * PKTSIZE_ALIGN) |
| 30 | #define TOTAL_PKT_BUF_SIZE (TX_TOTAL_BUF_SIZE + RX_TOTAL_BUF_SIZE) |
| 31 | |
| 32 | #define MT7530_NUM_PHYS 5 |
| 33 | #define MT7530_DFL_SMI_ADDR 31 |
| 34 | |
| 35 | #define MT7530_PHY_ADDR(base, addr) \ |
| 36 | (((base) + (addr)) & 0x1f) |
| 37 | |
| 38 | #define GDMA_FWD_TO_CPU \ |
| 39 | (0x20000000 | \ |
| 40 | GDM_ICS_EN | \ |
| 41 | GDM_TCS_EN | \ |
| 42 | GDM_UCS_EN | \ |
| 43 | STRP_CRC | \ |
| 44 | (DP_PDMA << MYMAC_DP_S) | \ |
| 45 | (DP_PDMA << BC_DP_S) | \ |
| 46 | (DP_PDMA << MC_DP_S) | \ |
| 47 | (DP_PDMA << UN_DP_S)) |
| 48 | |
| 49 | #define GDMA_FWD_DISCARD \ |
| 50 | (0x20000000 | \ |
| 51 | GDM_ICS_EN | \ |
| 52 | GDM_TCS_EN | \ |
| 53 | GDM_UCS_EN | \ |
| 54 | STRP_CRC | \ |
| 55 | (DP_DISCARD << MYMAC_DP_S) | \ |
| 56 | (DP_DISCARD << BC_DP_S) | \ |
| 57 | (DP_DISCARD << MC_DP_S) | \ |
| 58 | (DP_DISCARD << UN_DP_S)) |
| 59 | |
| 60 | struct pdma_rxd_info1 { |
| 61 | u32 PDP0; |
| 62 | }; |
| 63 | |
| 64 | struct pdma_rxd_info2 { |
| 65 | u32 PLEN1 : 14; |
| 66 | u32 LS1 : 1; |
| 67 | u32 UN_USED : 1; |
| 68 | u32 PLEN0 : 14; |
| 69 | u32 LS0 : 1; |
| 70 | u32 DDONE : 1; |
| 71 | }; |
| 72 | |
| 73 | struct pdma_rxd_info3 { |
| 74 | u32 PDP1; |
| 75 | }; |
| 76 | |
| 77 | struct pdma_rxd_info4 { |
| 78 | u32 FOE_ENTRY : 14; |
| 79 | u32 CRSN : 5; |
| 80 | u32 SP : 3; |
| 81 | u32 L4F : 1; |
| 82 | u32 L4VLD : 1; |
| 83 | u32 TACK : 1; |
| 84 | u32 IP4F : 1; |
| 85 | u32 IP4 : 1; |
| 86 | u32 IP6 : 1; |
| 87 | u32 UN_USED : 4; |
| 88 | }; |
| 89 | |
| 90 | struct pdma_rxdesc { |
| 91 | struct pdma_rxd_info1 rxd_info1; |
| 92 | struct pdma_rxd_info2 rxd_info2; |
| 93 | struct pdma_rxd_info3 rxd_info3; |
| 94 | struct pdma_rxd_info4 rxd_info4; |
| 95 | }; |
| 96 | |
| 97 | struct pdma_txd_info1 { |
| 98 | u32 SDP0; |
| 99 | }; |
| 100 | |
| 101 | struct pdma_txd_info2 { |
| 102 | u32 SDL1 : 14; |
| 103 | u32 LS1 : 1; |
| 104 | u32 BURST : 1; |
| 105 | u32 SDL0 : 14; |
| 106 | u32 LS0 : 1; |
| 107 | u32 DDONE : 1; |
| 108 | }; |
| 109 | |
| 110 | struct pdma_txd_info3 { |
| 111 | u32 SDP1; |
| 112 | }; |
| 113 | |
| 114 | struct pdma_txd_info4 { |
| 115 | u32 VLAN_TAG : 16; |
| 116 | u32 INS : 1; |
| 117 | u32 RESV : 2; |
| 118 | u32 UDF : 6; |
| 119 | u32 FPORT : 3; |
| 120 | u32 TSO : 1; |
| 121 | u32 TUI_CO : 3; |
| 122 | }; |
| 123 | |
| 124 | struct pdma_txdesc { |
| 125 | struct pdma_txd_info1 txd_info1; |
| 126 | struct pdma_txd_info2 txd_info2; |
| 127 | struct pdma_txd_info3 txd_info3; |
| 128 | struct pdma_txd_info4 txd_info4; |
| 129 | }; |
| 130 | |
| 131 | enum mtk_switch { |
| 132 | SW_NONE, |
| 133 | SW_MT7530 |
| 134 | }; |
| 135 | |
| 136 | enum mtk_soc { |
| 137 | SOC_MT7623, |
| 138 | SOC_MT7629 |
| 139 | }; |
| 140 | |
| 141 | struct mtk_eth_priv { |
| 142 | char pkt_pool[TOTAL_PKT_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN); |
| 143 | |
| 144 | struct pdma_txdesc *tx_ring_noc; |
| 145 | struct pdma_rxdesc *rx_ring_noc; |
| 146 | |
| 147 | int rx_dma_owner_idx0; |
| 148 | int tx_cpu_owner_idx0; |
| 149 | |
| 150 | void __iomem *fe_base; |
| 151 | void __iomem *gmac_base; |
| 152 | void __iomem *ethsys_base; |
| 153 | |
| 154 | struct mii_dev *mdio_bus; |
| 155 | int (*mii_read)(struct mtk_eth_priv *priv, u8 phy, u8 reg); |
| 156 | int (*mii_write)(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 val); |
| 157 | int (*mmd_read)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg); |
| 158 | int (*mmd_write)(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg, |
| 159 | u16 val); |
| 160 | |
| 161 | enum mtk_soc soc; |
| 162 | int gmac_id; |
| 163 | int force_mode; |
| 164 | int speed; |
| 165 | int duplex; |
| 166 | |
| 167 | struct phy_device *phydev; |
| 168 | int phy_interface; |
| 169 | int phy_addr; |
| 170 | |
| 171 | enum mtk_switch sw; |
| 172 | int (*switch_init)(struct mtk_eth_priv *priv); |
| 173 | u32 mt7530_smi_addr; |
| 174 | u32 mt7530_phy_base; |
| 175 | |
| 176 | struct gpio_desc rst_gpio; |
| 177 | int mcm; |
| 178 | |
| 179 | struct reset_ctl rst_fe; |
| 180 | struct reset_ctl rst_mcm; |
| 181 | }; |
| 182 | |
| 183 | static void mtk_pdma_write(struct mtk_eth_priv *priv, u32 reg, u32 val) |
| 184 | { |
| 185 | writel(val, priv->fe_base + PDMA_BASE + reg); |
| 186 | } |
| 187 | |
| 188 | static void mtk_pdma_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, |
| 189 | u32 set) |
| 190 | { |
| 191 | clrsetbits_le32(priv->fe_base + PDMA_BASE + reg, clr, set); |
| 192 | } |
| 193 | |
| 194 | static void mtk_gdma_write(struct mtk_eth_priv *priv, int no, u32 reg, |
| 195 | u32 val) |
| 196 | { |
| 197 | u32 gdma_base; |
| 198 | |
| 199 | if (no == 1) |
| 200 | gdma_base = GDMA2_BASE; |
| 201 | else |
| 202 | gdma_base = GDMA1_BASE; |
| 203 | |
| 204 | writel(val, priv->fe_base + gdma_base + reg); |
| 205 | } |
| 206 | |
| 207 | static u32 mtk_gmac_read(struct mtk_eth_priv *priv, u32 reg) |
| 208 | { |
| 209 | return readl(priv->gmac_base + reg); |
| 210 | } |
| 211 | |
| 212 | static void mtk_gmac_write(struct mtk_eth_priv *priv, u32 reg, u32 val) |
| 213 | { |
| 214 | writel(val, priv->gmac_base + reg); |
| 215 | } |
| 216 | |
| 217 | static void mtk_gmac_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, u32 set) |
| 218 | { |
| 219 | clrsetbits_le32(priv->gmac_base + reg, clr, set); |
| 220 | } |
| 221 | |
| 222 | static void mtk_ethsys_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, |
| 223 | u32 set) |
| 224 | { |
| 225 | clrsetbits_le32(priv->ethsys_base + reg, clr, set); |
| 226 | } |
| 227 | |
| 228 | /* Direct MDIO clause 22/45 access via SoC */ |
| 229 | static int mtk_mii_rw(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data, |
| 230 | u32 cmd, u32 st) |
| 231 | { |
| 232 | int ret; |
| 233 | u32 val; |
| 234 | |
| 235 | val = (st << MDIO_ST_S) | |
| 236 | ((cmd << MDIO_CMD_S) & MDIO_CMD_M) | |
| 237 | (((u32)phy << MDIO_PHY_ADDR_S) & MDIO_PHY_ADDR_M) | |
| 238 | (((u32)reg << MDIO_REG_ADDR_S) & MDIO_REG_ADDR_M); |
| 239 | |
| 240 | if (cmd == MDIO_CMD_WRITE) |
| 241 | val |= data & MDIO_RW_DATA_M; |
| 242 | |
| 243 | mtk_gmac_write(priv, GMAC_PIAC_REG, val | PHY_ACS_ST); |
| 244 | |
| 245 | ret = wait_for_bit_le32(priv->gmac_base + GMAC_PIAC_REG, |
| 246 | PHY_ACS_ST, 0, 5000, 0); |
| 247 | if (ret) { |
| 248 | pr_warn("MDIO access timeout\n"); |
| 249 | return ret; |
| 250 | } |
| 251 | |
| 252 | if (cmd == MDIO_CMD_READ) { |
| 253 | val = mtk_gmac_read(priv, GMAC_PIAC_REG); |
| 254 | return val & MDIO_RW_DATA_M; |
| 255 | } |
| 256 | |
| 257 | return 0; |
| 258 | } |
| 259 | |
| 260 | /* Direct MDIO clause 22 read via SoC */ |
| 261 | static int mtk_mii_read(struct mtk_eth_priv *priv, u8 phy, u8 reg) |
| 262 | { |
| 263 | return mtk_mii_rw(priv, phy, reg, 0, MDIO_CMD_READ, MDIO_ST_C22); |
| 264 | } |
| 265 | |
| 266 | /* Direct MDIO clause 22 write via SoC */ |
| 267 | static int mtk_mii_write(struct mtk_eth_priv *priv, u8 phy, u8 reg, u16 data) |
| 268 | { |
| 269 | return mtk_mii_rw(priv, phy, reg, data, MDIO_CMD_WRITE, MDIO_ST_C22); |
| 270 | } |
| 271 | |
| 272 | /* Direct MDIO clause 45 read via SoC */ |
| 273 | static int mtk_mmd_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, u16 reg) |
| 274 | { |
| 275 | int ret; |
| 276 | |
| 277 | ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); |
| 278 | if (ret) |
| 279 | return ret; |
| 280 | |
| 281 | return mtk_mii_rw(priv, addr, devad, 0, MDIO_CMD_READ_C45, |
| 282 | MDIO_ST_C45); |
| 283 | } |
| 284 | |
| 285 | /* Direct MDIO clause 45 write via SoC */ |
| 286 | static int mtk_mmd_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, |
| 287 | u16 reg, u16 val) |
| 288 | { |
| 289 | int ret; |
| 290 | |
| 291 | ret = mtk_mii_rw(priv, addr, devad, reg, MDIO_CMD_ADDR, MDIO_ST_C45); |
| 292 | if (ret) |
| 293 | return ret; |
| 294 | |
| 295 | return mtk_mii_rw(priv, addr, devad, val, MDIO_CMD_WRITE, |
| 296 | MDIO_ST_C45); |
| 297 | } |
| 298 | |
| 299 | /* Indirect MDIO clause 45 read via MII registers */ |
| 300 | static int mtk_mmd_ind_read(struct mtk_eth_priv *priv, u8 addr, u8 devad, |
| 301 | u16 reg) |
| 302 | { |
| 303 | int ret; |
| 304 | |
| 305 | ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, |
| 306 | (MMD_ADDR << MMD_CMD_S) | |
| 307 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); |
| 308 | if (ret) |
| 309 | return ret; |
| 310 | |
| 311 | ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); |
| 312 | if (ret) |
| 313 | return ret; |
| 314 | |
| 315 | ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, |
| 316 | (MMD_DATA << MMD_CMD_S) | |
| 317 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); |
| 318 | if (ret) |
| 319 | return ret; |
| 320 | |
| 321 | return priv->mii_read(priv, addr, MII_MMD_ADDR_DATA_REG); |
| 322 | } |
| 323 | |
| 324 | /* Indirect MDIO clause 45 write via MII registers */ |
| 325 | static int mtk_mmd_ind_write(struct mtk_eth_priv *priv, u8 addr, u8 devad, |
| 326 | u16 reg, u16 val) |
| 327 | { |
| 328 | int ret; |
| 329 | |
| 330 | ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, |
| 331 | (MMD_ADDR << MMD_CMD_S) | |
| 332 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); |
| 333 | if (ret) |
| 334 | return ret; |
| 335 | |
| 336 | ret = priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, reg); |
| 337 | if (ret) |
| 338 | return ret; |
| 339 | |
| 340 | ret = priv->mii_write(priv, addr, MII_MMD_ACC_CTL_REG, |
| 341 | (MMD_DATA << MMD_CMD_S) | |
| 342 | ((devad << MMD_DEVAD_S) & MMD_DEVAD_M)); |
| 343 | if (ret) |
| 344 | return ret; |
| 345 | |
| 346 | return priv->mii_write(priv, addr, MII_MMD_ADDR_DATA_REG, val); |
| 347 | } |
| 348 | |
| 349 | static int mtk_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
| 350 | { |
| 351 | struct mtk_eth_priv *priv = bus->priv; |
| 352 | |
| 353 | if (devad < 0) |
| 354 | return priv->mii_read(priv, addr, reg); |
| 355 | else |
| 356 | return priv->mmd_read(priv, addr, devad, reg); |
| 357 | } |
| 358 | |
| 359 | static int mtk_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
| 360 | u16 val) |
| 361 | { |
| 362 | struct mtk_eth_priv *priv = bus->priv; |
| 363 | |
| 364 | if (devad < 0) |
| 365 | return priv->mii_write(priv, addr, reg, val); |
| 366 | else |
| 367 | return priv->mmd_write(priv, addr, devad, reg, val); |
| 368 | } |
| 369 | |
| 370 | static int mtk_mdio_register(struct udevice *dev) |
| 371 | { |
| 372 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 373 | struct mii_dev *mdio_bus = mdio_alloc(); |
| 374 | int ret; |
| 375 | |
| 376 | if (!mdio_bus) |
| 377 | return -ENOMEM; |
| 378 | |
| 379 | /* Assign MDIO access APIs according to the switch/phy */ |
| 380 | switch (priv->sw) { |
| 381 | case SW_MT7530: |
| 382 | priv->mii_read = mtk_mii_read; |
| 383 | priv->mii_write = mtk_mii_write; |
| 384 | priv->mmd_read = mtk_mmd_ind_read; |
| 385 | priv->mmd_write = mtk_mmd_ind_write; |
| 386 | break; |
| 387 | default: |
| 388 | priv->mii_read = mtk_mii_read; |
| 389 | priv->mii_write = mtk_mii_write; |
| 390 | priv->mmd_read = mtk_mmd_read; |
| 391 | priv->mmd_write = mtk_mmd_write; |
| 392 | } |
| 393 | |
| 394 | mdio_bus->read = mtk_mdio_read; |
| 395 | mdio_bus->write = mtk_mdio_write; |
| 396 | snprintf(mdio_bus->name, sizeof(mdio_bus->name), dev->name); |
| 397 | |
| 398 | mdio_bus->priv = (void *)priv; |
| 399 | |
| 400 | ret = mdio_register(mdio_bus); |
| 401 | |
| 402 | if (ret) |
| 403 | return ret; |
| 404 | |
| 405 | priv->mdio_bus = mdio_bus; |
| 406 | |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | /* |
| 411 | * MT7530 Internal Register Address Bits |
| 412 | * ------------------------------------------------------------------- |
| 413 | * | 15 14 13 12 11 10 9 8 7 6 | 5 4 3 2 | 1 0 | |
| 414 | * |----------------------------------------|---------------|--------| |
| 415 | * | Page Address | Reg Address | Unused | |
| 416 | * ------------------------------------------------------------------- |
| 417 | */ |
| 418 | |
| 419 | static int mt7530_reg_read(struct mtk_eth_priv *priv, u32 reg, u32 *data) |
| 420 | { |
| 421 | int ret, low_word, high_word; |
| 422 | |
| 423 | /* Write page address */ |
| 424 | ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6); |
| 425 | if (ret) |
| 426 | return ret; |
| 427 | |
| 428 | /* Read low word */ |
| 429 | low_word = mtk_mii_read(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf); |
| 430 | if (low_word < 0) |
| 431 | return low_word; |
| 432 | |
| 433 | /* Read high word */ |
| 434 | high_word = mtk_mii_read(priv, priv->mt7530_smi_addr, 0x10); |
| 435 | if (high_word < 0) |
| 436 | return high_word; |
| 437 | |
| 438 | if (data) |
| 439 | *data = ((u32)high_word << 16) | (low_word & 0xffff); |
| 440 | |
| 441 | return 0; |
| 442 | } |
| 443 | |
| 444 | static int mt7530_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 data) |
| 445 | { |
| 446 | int ret; |
| 447 | |
| 448 | /* Write page address */ |
| 449 | ret = mtk_mii_write(priv, priv->mt7530_smi_addr, 0x1f, reg >> 6); |
| 450 | if (ret) |
| 451 | return ret; |
| 452 | |
| 453 | /* Write low word */ |
| 454 | ret = mtk_mii_write(priv, priv->mt7530_smi_addr, (reg >> 2) & 0xf, |
| 455 | data & 0xffff); |
| 456 | if (ret) |
| 457 | return ret; |
| 458 | |
| 459 | /* Write high word */ |
| 460 | return mtk_mii_write(priv, priv->mt7530_smi_addr, 0x10, data >> 16); |
| 461 | } |
| 462 | |
| 463 | static void mt7530_reg_rmw(struct mtk_eth_priv *priv, u32 reg, u32 clr, |
| 464 | u32 set) |
| 465 | { |
| 466 | u32 val; |
| 467 | |
| 468 | mt7530_reg_read(priv, reg, &val); |
| 469 | val &= ~clr; |
| 470 | val |= set; |
| 471 | mt7530_reg_write(priv, reg, val); |
| 472 | } |
| 473 | |
| 474 | static void mt7530_core_reg_write(struct mtk_eth_priv *priv, u32 reg, u32 val) |
| 475 | { |
| 476 | u8 phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, 0); |
| 477 | |
| 478 | mtk_mmd_ind_write(priv, phy_addr, 0x1f, reg, val); |
| 479 | } |
| 480 | |
| 481 | static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode) |
| 482 | { |
| 483 | u32 ncpo1, ssc_delta; |
| 484 | |
| 485 | switch (mode) { |
| 486 | case PHY_INTERFACE_MODE_RGMII: |
| 487 | ncpo1 = 0x0c80; |
| 488 | ssc_delta = 0x87; |
| 489 | break; |
| 490 | default: |
| 491 | printf("error: xMII mode %d not supported\n", mode); |
| 492 | return -EINVAL; |
| 493 | } |
| 494 | |
| 495 | /* Disable MT7530 core clock */ |
| 496 | mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, 0); |
| 497 | |
| 498 | /* Disable MT7530 PLL */ |
| 499 | mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, |
| 500 | (2 << RG_GSWPLL_POSDIV_200M_S) | |
| 501 | (32 << RG_GSWPLL_FBKDIV_200M_S)); |
| 502 | |
| 503 | /* For MT7530 core clock = 500Mhz */ |
| 504 | mt7530_core_reg_write(priv, CORE_GSWPLL_GRP2, |
| 505 | (1 << RG_GSWPLL_POSDIV_500M_S) | |
| 506 | (25 << RG_GSWPLL_FBKDIV_500M_S)); |
| 507 | |
| 508 | /* Enable MT7530 PLL */ |
| 509 | mt7530_core_reg_write(priv, CORE_GSWPLL_GRP1, |
| 510 | (2 << RG_GSWPLL_POSDIV_200M_S) | |
| 511 | (32 << RG_GSWPLL_FBKDIV_200M_S) | |
| 512 | RG_GSWPLL_EN_PRE); |
| 513 | |
| 514 | udelay(20); |
| 515 | |
| 516 | mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); |
| 517 | |
| 518 | /* Setup the MT7530 TRGMII Tx Clock */ |
| 519 | mt7530_core_reg_write(priv, CORE_PLL_GROUP5, ncpo1); |
| 520 | mt7530_core_reg_write(priv, CORE_PLL_GROUP6, 0); |
| 521 | mt7530_core_reg_write(priv, CORE_PLL_GROUP10, ssc_delta); |
| 522 | mt7530_core_reg_write(priv, CORE_PLL_GROUP11, ssc_delta); |
| 523 | mt7530_core_reg_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | |
| 524 | RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); |
| 525 | |
| 526 | mt7530_core_reg_write(priv, CORE_PLL_GROUP2, |
| 527 | RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | |
| 528 | (1 << RG_SYSPLL_POSDIV_S)); |
| 529 | |
| 530 | mt7530_core_reg_write(priv, CORE_PLL_GROUP7, |
| 531 | RG_LCDDS_PCW_NCPO_CHG | (3 << RG_LCCDS_C_S) | |
| 532 | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); |
| 533 | |
| 534 | /* Enable MT7530 core clock */ |
| 535 | mt7530_core_reg_write(priv, CORE_TRGMII_GSW_CLK_CG, |
| 536 | REG_GSWCK_EN | REG_TRGMIICK_EN); |
| 537 | |
| 538 | return 0; |
| 539 | } |
| 540 | |
| 541 | static int mt7530_setup(struct mtk_eth_priv *priv) |
| 542 | { |
| 543 | u16 phy_addr, phy_val; |
| 544 | u32 val; |
| 545 | int i; |
| 546 | |
| 547 | /* Select 250MHz clk for RGMII mode */ |
| 548 | mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG, |
| 549 | ETHSYS_TRGMII_CLK_SEL362_5, 0); |
| 550 | |
| 551 | /* Global reset switch */ |
| 552 | if (priv->mcm) { |
| 553 | reset_assert(&priv->rst_mcm); |
| 554 | udelay(1000); |
| 555 | reset_deassert(&priv->rst_mcm); |
| 556 | mdelay(1000); |
| 557 | } else if (dm_gpio_is_valid(&priv->rst_gpio)) { |
| 558 | dm_gpio_set_value(&priv->rst_gpio, 0); |
| 559 | udelay(1000); |
| 560 | dm_gpio_set_value(&priv->rst_gpio, 1); |
| 561 | mdelay(1000); |
| 562 | } |
| 563 | |
| 564 | /* Modify HWTRAP first to allow direct access to internal PHYs */ |
| 565 | mt7530_reg_read(priv, HWTRAP_REG, &val); |
| 566 | val |= CHG_TRAP; |
| 567 | val &= ~C_MDIO_BPS; |
| 568 | mt7530_reg_write(priv, MHWTRAP_REG, val); |
| 569 | |
| 570 | /* Calculate the phy base address */ |
| 571 | val = ((val & SMI_ADDR_M) >> SMI_ADDR_S) << 3; |
| 572 | priv->mt7530_phy_base = (val | 0x7) + 1; |
| 573 | |
| 574 | /* Turn off PHYs */ |
| 575 | for (i = 0; i < MT7530_NUM_PHYS; i++) { |
| 576 | phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i); |
| 577 | phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); |
| 578 | phy_val |= BMCR_PDOWN; |
| 579 | priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); |
| 580 | } |
| 581 | |
| 582 | /* Force MAC link down before reset */ |
| 583 | mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE); |
| 584 | mt7530_reg_write(priv, PCMR_REG(6), FORCE_MODE); |
| 585 | |
| 586 | /* MT7530 reset */ |
| 587 | mt7530_reg_write(priv, SYS_CTRL_REG, SW_SYS_RST | SW_REG_RST); |
| 588 | udelay(100); |
| 589 | |
| 590 | val = (1 << IPG_CFG_S) | |
| 591 | MAC_MODE | FORCE_MODE | |
| 592 | MAC_TX_EN | MAC_RX_EN | |
| 593 | BKOFF_EN | BACKPR_EN | |
| 594 | (SPEED_1000M << FORCE_SPD_S) | |
| 595 | FORCE_DPX | FORCE_LINK; |
| 596 | |
| 597 | /* MT7530 Port6: Forced 1000M/FD, FC disabled */ |
| 598 | mt7530_reg_write(priv, PCMR_REG(6), val); |
| 599 | |
| 600 | /* MT7530 Port5: Forced link down */ |
| 601 | mt7530_reg_write(priv, PCMR_REG(5), FORCE_MODE); |
| 602 | |
| 603 | /* MT7530 Port6: Set to RGMII */ |
| 604 | mt7530_reg_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_M, P6_INTF_MODE_RGMII); |
| 605 | |
| 606 | /* Hardware Trap: Enable Port6, Disable Port5 */ |
| 607 | mt7530_reg_read(priv, HWTRAP_REG, &val); |
| 608 | val |= CHG_TRAP | LOOPDET_DIS | P5_INTF_DIS | |
| 609 | (P5_INTF_SEL_GMAC5 << P5_INTF_SEL_S) | |
| 610 | (P5_INTF_MODE_RGMII << P5_INTF_MODE_S); |
| 611 | val &= ~(C_MDIO_BPS | P6_INTF_DIS); |
| 612 | mt7530_reg_write(priv, MHWTRAP_REG, val); |
| 613 | |
| 614 | /* Setup switch core pll */ |
| 615 | mt7530_pad_clk_setup(priv, priv->phy_interface); |
| 616 | |
| 617 | /* Lower Tx Driving for TRGMII path */ |
| 618 | for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) |
| 619 | mt7530_reg_write(priv, MT7530_TRGMII_TD_ODT(i), |
| 620 | (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S)); |
| 621 | |
| 622 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) |
| 623 | mt7530_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16); |
| 624 | |
| 625 | /* Turn on PHYs */ |
| 626 | for (i = 0; i < MT7530_NUM_PHYS; i++) { |
| 627 | phy_addr = MT7530_PHY_ADDR(priv->mt7530_phy_base, i); |
| 628 | phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); |
| 629 | phy_val &= ~BMCR_PDOWN; |
| 630 | priv->mii_write(priv, phy_addr, MII_BMCR, phy_val); |
| 631 | } |
| 632 | |
| 633 | /* Set port isolation */ |
| 634 | for (i = 0; i < 8; i++) { |
| 635 | /* Set port matrix mode */ |
| 636 | if (i != 6) |
| 637 | mt7530_reg_write(priv, PCR_REG(i), |
| 638 | (0x40 << PORT_MATRIX_S)); |
| 639 | else |
| 640 | mt7530_reg_write(priv, PCR_REG(i), |
| 641 | (0x3f << PORT_MATRIX_S)); |
| 642 | |
| 643 | /* Set port mode to user port */ |
| 644 | mt7530_reg_write(priv, PVC_REG(i), |
| 645 | (0x8100 << STAG_VPID_S) | |
| 646 | (VLAN_ATTR_USER << VLAN_ATTR_S)); |
| 647 | } |
| 648 | |
| 649 | return 0; |
| 650 | } |
| 651 | |
| 652 | static void mtk_phy_link_adjust(struct mtk_eth_priv *priv) |
| 653 | { |
| 654 | u16 lcl_adv = 0, rmt_adv = 0; |
| 655 | u8 flowctrl; |
| 656 | u32 mcr; |
| 657 | |
| 658 | mcr = (1 << IPG_CFG_S) | |
| 659 | (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | |
| 660 | MAC_MODE | FORCE_MODE | |
| 661 | MAC_TX_EN | MAC_RX_EN | |
| 662 | BKOFF_EN | BACKPR_EN; |
| 663 | |
| 664 | switch (priv->phydev->speed) { |
| 665 | case SPEED_10: |
| 666 | mcr |= (SPEED_10M << FORCE_SPD_S); |
| 667 | break; |
| 668 | case SPEED_100: |
| 669 | mcr |= (SPEED_100M << FORCE_SPD_S); |
| 670 | break; |
| 671 | case SPEED_1000: |
| 672 | mcr |= (SPEED_1000M << FORCE_SPD_S); |
| 673 | break; |
| 674 | }; |
| 675 | |
| 676 | if (priv->phydev->link) |
| 677 | mcr |= FORCE_LINK; |
| 678 | |
| 679 | if (priv->phydev->duplex) { |
| 680 | mcr |= FORCE_DPX; |
| 681 | |
| 682 | if (priv->phydev->pause) |
| 683 | rmt_adv = LPA_PAUSE_CAP; |
| 684 | if (priv->phydev->asym_pause) |
| 685 | rmt_adv |= LPA_PAUSE_ASYM; |
| 686 | |
| 687 | if (priv->phydev->advertising & ADVERTISED_Pause) |
| 688 | lcl_adv |= ADVERTISE_PAUSE_CAP; |
| 689 | if (priv->phydev->advertising & ADVERTISED_Asym_Pause) |
| 690 | lcl_adv |= ADVERTISE_PAUSE_ASYM; |
| 691 | |
| 692 | flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); |
| 693 | |
| 694 | if (flowctrl & FLOW_CTRL_TX) |
| 695 | mcr |= FORCE_TX_FC; |
| 696 | if (flowctrl & FLOW_CTRL_RX) |
| 697 | mcr |= FORCE_RX_FC; |
| 698 | |
| 699 | debug("rx pause %s, tx pause %s\n", |
| 700 | flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", |
| 701 | flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); |
| 702 | } |
| 703 | |
| 704 | mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); |
| 705 | } |
| 706 | |
| 707 | static int mtk_phy_start(struct mtk_eth_priv *priv) |
| 708 | { |
| 709 | struct phy_device *phydev = priv->phydev; |
| 710 | int ret; |
| 711 | |
| 712 | ret = phy_startup(phydev); |
| 713 | |
| 714 | if (ret) { |
| 715 | debug("Could not initialize PHY %s\n", phydev->dev->name); |
| 716 | return ret; |
| 717 | } |
| 718 | |
| 719 | if (!phydev->link) { |
| 720 | debug("%s: link down.\n", phydev->dev->name); |
| 721 | return 0; |
| 722 | } |
| 723 | |
| 724 | mtk_phy_link_adjust(priv); |
| 725 | |
| 726 | debug("Speed: %d, %s duplex%s\n", phydev->speed, |
| 727 | (phydev->duplex) ? "full" : "half", |
| 728 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); |
| 729 | |
| 730 | return 0; |
| 731 | } |
| 732 | |
| 733 | static int mtk_phy_probe(struct udevice *dev) |
| 734 | { |
| 735 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 736 | struct phy_device *phydev; |
| 737 | |
| 738 | phydev = phy_connect(priv->mdio_bus, priv->phy_addr, dev, |
| 739 | priv->phy_interface); |
| 740 | if (!phydev) |
| 741 | return -ENODEV; |
| 742 | |
| 743 | phydev->supported &= PHY_GBIT_FEATURES; |
| 744 | phydev->advertising = phydev->supported; |
| 745 | |
| 746 | priv->phydev = phydev; |
| 747 | phy_config(phydev); |
| 748 | |
| 749 | return 0; |
| 750 | } |
| 751 | |
| 752 | static void mtk_mac_init(struct mtk_eth_priv *priv) |
| 753 | { |
| 754 | int i, ge_mode = 0; |
| 755 | u32 mcr; |
| 756 | |
| 757 | switch (priv->phy_interface) { |
| 758 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 759 | case PHY_INTERFACE_MODE_RGMII: |
| 760 | case PHY_INTERFACE_MODE_SGMII: |
| 761 | ge_mode = GE_MODE_RGMII; |
| 762 | break; |
| 763 | case PHY_INTERFACE_MODE_MII: |
| 764 | case PHY_INTERFACE_MODE_GMII: |
| 765 | ge_mode = GE_MODE_MII; |
| 766 | break; |
| 767 | case PHY_INTERFACE_MODE_RMII: |
| 768 | ge_mode = GE_MODE_RMII; |
| 769 | break; |
| 770 | default: |
| 771 | break; |
| 772 | } |
| 773 | |
| 774 | /* set the gmac to the right mode */ |
| 775 | mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, |
| 776 | SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id), |
| 777 | ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id)); |
| 778 | |
| 779 | if (priv->force_mode) { |
| 780 | mcr = (1 << IPG_CFG_S) | |
| 781 | (MAC_RX_PKT_LEN_1536 << MAC_RX_PKT_LEN_S) | |
| 782 | MAC_MODE | FORCE_MODE | |
| 783 | MAC_TX_EN | MAC_RX_EN | |
| 784 | BKOFF_EN | BACKPR_EN | |
| 785 | FORCE_LINK; |
| 786 | |
| 787 | switch (priv->speed) { |
| 788 | case SPEED_10: |
| 789 | mcr |= SPEED_10M << FORCE_SPD_S; |
| 790 | break; |
| 791 | case SPEED_100: |
| 792 | mcr |= SPEED_100M << FORCE_SPD_S; |
| 793 | break; |
| 794 | case SPEED_1000: |
| 795 | mcr |= SPEED_1000M << FORCE_SPD_S; |
| 796 | break; |
| 797 | } |
| 798 | |
| 799 | if (priv->duplex) |
| 800 | mcr |= FORCE_DPX; |
| 801 | |
| 802 | mtk_gmac_write(priv, GMAC_PORT_MCR(priv->gmac_id), mcr); |
| 803 | } |
| 804 | |
| 805 | if (priv->soc == SOC_MT7623) { |
| 806 | /* Lower Tx Driving for TRGMII path */ |
| 807 | for (i = 0 ; i < NUM_TRGMII_CTRL; i++) |
| 808 | mtk_gmac_write(priv, GMAC_TRGMII_TD_ODT(i), |
| 809 | (8 << TD_DM_DRVP_S) | |
| 810 | (8 << TD_DM_DRVN_S)); |
| 811 | |
| 812 | mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, 0, |
| 813 | RX_RST | RXC_DQSISEL); |
| 814 | mtk_gmac_rmw(priv, GMAC_TRGMII_RCK_CTRL, RX_RST, 0); |
| 815 | } |
| 816 | } |
| 817 | |
| 818 | static void mtk_eth_fifo_init(struct mtk_eth_priv *priv) |
| 819 | { |
| 820 | char *pkt_base = priv->pkt_pool; |
| 821 | int i; |
| 822 | |
| 823 | mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0xffff0000, 0); |
| 824 | udelay(500); |
| 825 | |
| 826 | memset(priv->tx_ring_noc, 0, NUM_TX_DESC * sizeof(struct pdma_txdesc)); |
| 827 | memset(priv->rx_ring_noc, 0, NUM_RX_DESC * sizeof(struct pdma_rxdesc)); |
| 828 | memset(priv->pkt_pool, 0, TOTAL_PKT_BUF_SIZE); |
| 829 | |
| 830 | flush_dcache_range((u32)pkt_base, (u32)(pkt_base + TOTAL_PKT_BUF_SIZE)); |
| 831 | |
| 832 | priv->rx_dma_owner_idx0 = 0; |
| 833 | priv->tx_cpu_owner_idx0 = 0; |
| 834 | |
| 835 | for (i = 0; i < NUM_TX_DESC; i++) { |
| 836 | priv->tx_ring_noc[i].txd_info2.LS0 = 1; |
| 837 | priv->tx_ring_noc[i].txd_info2.DDONE = 1; |
| 838 | priv->tx_ring_noc[i].txd_info4.FPORT = priv->gmac_id + 1; |
| 839 | |
| 840 | priv->tx_ring_noc[i].txd_info1.SDP0 = virt_to_phys(pkt_base); |
| 841 | pkt_base += PKTSIZE_ALIGN; |
| 842 | } |
| 843 | |
| 844 | for (i = 0; i < NUM_RX_DESC; i++) { |
| 845 | priv->rx_ring_noc[i].rxd_info2.PLEN0 = PKTSIZE_ALIGN; |
| 846 | priv->rx_ring_noc[i].rxd_info1.PDP0 = virt_to_phys(pkt_base); |
| 847 | pkt_base += PKTSIZE_ALIGN; |
| 848 | } |
| 849 | |
| 850 | mtk_pdma_write(priv, TX_BASE_PTR_REG(0), |
| 851 | virt_to_phys(priv->tx_ring_noc)); |
| 852 | mtk_pdma_write(priv, TX_MAX_CNT_REG(0), NUM_TX_DESC); |
| 853 | mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); |
| 854 | |
| 855 | mtk_pdma_write(priv, RX_BASE_PTR_REG(0), |
| 856 | virt_to_phys(priv->rx_ring_noc)); |
| 857 | mtk_pdma_write(priv, RX_MAX_CNT_REG(0), NUM_RX_DESC); |
| 858 | mtk_pdma_write(priv, RX_CRX_IDX_REG(0), NUM_RX_DESC - 1); |
| 859 | |
| 860 | mtk_pdma_write(priv, PDMA_RST_IDX_REG, RST_DTX_IDX0 | RST_DRX_IDX0); |
| 861 | } |
| 862 | |
| 863 | static int mtk_eth_start(struct udevice *dev) |
| 864 | { |
| 865 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 866 | int ret; |
| 867 | |
| 868 | /* Reset FE */ |
| 869 | reset_assert(&priv->rst_fe); |
| 870 | udelay(1000); |
| 871 | reset_deassert(&priv->rst_fe); |
| 872 | mdelay(10); |
| 873 | |
| 874 | /* Packets forward to PDMA */ |
| 875 | mtk_gdma_write(priv, priv->gmac_id, GDMA_IG_CTRL_REG, GDMA_FWD_TO_CPU); |
| 876 | |
| 877 | if (priv->gmac_id == 0) |
| 878 | mtk_gdma_write(priv, 1, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); |
| 879 | else |
| 880 | mtk_gdma_write(priv, 0, GDMA_IG_CTRL_REG, GDMA_FWD_DISCARD); |
| 881 | |
| 882 | udelay(500); |
| 883 | |
| 884 | mtk_eth_fifo_init(priv); |
| 885 | |
| 886 | /* Start PHY */ |
| 887 | if (priv->sw == SW_NONE) { |
| 888 | ret = mtk_phy_start(priv); |
| 889 | if (ret) |
| 890 | return ret; |
| 891 | } |
| 892 | |
| 893 | mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, 0, |
| 894 | TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN); |
| 895 | udelay(500); |
| 896 | |
| 897 | return 0; |
| 898 | } |
| 899 | |
| 900 | static void mtk_eth_stop(struct udevice *dev) |
| 901 | { |
| 902 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 903 | |
| 904 | mtk_pdma_rmw(priv, PDMA_GLO_CFG_REG, |
| 905 | TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN, 0); |
| 906 | udelay(500); |
| 907 | |
| 908 | wait_for_bit_le32(priv->fe_base + PDMA_BASE + PDMA_GLO_CFG_REG, |
| 909 | RX_DMA_BUSY | TX_DMA_BUSY, 0, 5000, 0); |
| 910 | } |
| 911 | |
| 912 | static int mtk_eth_write_hwaddr(struct udevice *dev) |
| 913 | { |
| 914 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 915 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 916 | unsigned char *mac = pdata->enetaddr; |
| 917 | u32 macaddr_lsb, macaddr_msb; |
| 918 | |
| 919 | macaddr_msb = ((u32)mac[0] << 8) | (u32)mac[1]; |
| 920 | macaddr_lsb = ((u32)mac[2] << 24) | ((u32)mac[3] << 16) | |
| 921 | ((u32)mac[4] << 8) | (u32)mac[5]; |
| 922 | |
| 923 | mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_MSB_REG, macaddr_msb); |
| 924 | mtk_gdma_write(priv, priv->gmac_id, GDMA_MAC_LSB_REG, macaddr_lsb); |
| 925 | |
| 926 | return 0; |
| 927 | } |
| 928 | |
| 929 | static int mtk_eth_send(struct udevice *dev, void *packet, int length) |
| 930 | { |
| 931 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 932 | u32 idx = priv->tx_cpu_owner_idx0; |
| 933 | void *pkt_base; |
| 934 | |
| 935 | if (!priv->tx_ring_noc[idx].txd_info2.DDONE) { |
| 936 | debug("mtk-eth: TX DMA descriptor ring is full\n"); |
| 937 | return -EPERM; |
| 938 | } |
| 939 | |
| 940 | pkt_base = (void *)phys_to_virt(priv->tx_ring_noc[idx].txd_info1.SDP0); |
| 941 | memcpy(pkt_base, packet, length); |
| 942 | flush_dcache_range((u32)pkt_base, (u32)pkt_base + |
| 943 | roundup(length, ARCH_DMA_MINALIGN)); |
| 944 | |
| 945 | priv->tx_ring_noc[idx].txd_info2.SDL0 = length; |
| 946 | priv->tx_ring_noc[idx].txd_info2.DDONE = 0; |
| 947 | |
| 948 | priv->tx_cpu_owner_idx0 = (priv->tx_cpu_owner_idx0 + 1) % NUM_TX_DESC; |
| 949 | mtk_pdma_write(priv, TX_CTX_IDX_REG(0), priv->tx_cpu_owner_idx0); |
| 950 | |
| 951 | return 0; |
| 952 | } |
| 953 | |
| 954 | static int mtk_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
| 955 | { |
| 956 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 957 | u32 idx = priv->rx_dma_owner_idx0; |
| 958 | uchar *pkt_base; |
| 959 | u32 length; |
| 960 | |
| 961 | if (!priv->rx_ring_noc[idx].rxd_info2.DDONE) { |
| 962 | debug("mtk-eth: RX DMA descriptor ring is empty\n"); |
| 963 | return -EAGAIN; |
| 964 | } |
| 965 | |
| 966 | length = priv->rx_ring_noc[idx].rxd_info2.PLEN0; |
| 967 | pkt_base = (void *)phys_to_virt(priv->rx_ring_noc[idx].rxd_info1.PDP0); |
| 968 | invalidate_dcache_range((u32)pkt_base, (u32)pkt_base + |
| 969 | roundup(length, ARCH_DMA_MINALIGN)); |
| 970 | |
| 971 | if (packetp) |
| 972 | *packetp = pkt_base; |
| 973 | |
| 974 | return length; |
| 975 | } |
| 976 | |
| 977 | static int mtk_eth_free_pkt(struct udevice *dev, uchar *packet, int length) |
| 978 | { |
| 979 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 980 | u32 idx = priv->rx_dma_owner_idx0; |
| 981 | |
| 982 | priv->rx_ring_noc[idx].rxd_info2.DDONE = 0; |
| 983 | priv->rx_ring_noc[idx].rxd_info2.LS0 = 0; |
| 984 | priv->rx_ring_noc[idx].rxd_info2.PLEN0 = PKTSIZE_ALIGN; |
| 985 | |
| 986 | mtk_pdma_write(priv, RX_CRX_IDX_REG(0), idx); |
| 987 | priv->rx_dma_owner_idx0 = (priv->rx_dma_owner_idx0 + 1) % NUM_RX_DESC; |
| 988 | |
| 989 | return 0; |
| 990 | } |
| 991 | |
| 992 | static int mtk_eth_probe(struct udevice *dev) |
| 993 | { |
| 994 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 995 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 996 | u32 iobase = pdata->iobase; |
| 997 | int ret; |
| 998 | |
| 999 | /* Frame Engine Register Base */ |
| 1000 | priv->fe_base = (void *)iobase; |
| 1001 | |
| 1002 | /* GMAC Register Base */ |
| 1003 | priv->gmac_base = (void *)(iobase + GMAC_BASE); |
| 1004 | |
| 1005 | /* MDIO register */ |
| 1006 | ret = mtk_mdio_register(dev); |
| 1007 | if (ret) |
| 1008 | return ret; |
| 1009 | |
| 1010 | /* Prepare for tx/rx rings */ |
| 1011 | priv->tx_ring_noc = (struct pdma_txdesc *) |
| 1012 | noncached_alloc(sizeof(struct pdma_txdesc) * NUM_TX_DESC, |
| 1013 | ARCH_DMA_MINALIGN); |
| 1014 | priv->rx_ring_noc = (struct pdma_rxdesc *) |
| 1015 | noncached_alloc(sizeof(struct pdma_rxdesc) * NUM_RX_DESC, |
| 1016 | ARCH_DMA_MINALIGN); |
| 1017 | |
| 1018 | /* Set MAC mode */ |
| 1019 | mtk_mac_init(priv); |
| 1020 | |
| 1021 | /* Probe phy if switch is not specified */ |
| 1022 | if (priv->sw == SW_NONE) |
| 1023 | return mtk_phy_probe(dev); |
| 1024 | |
| 1025 | /* Initialize switch */ |
| 1026 | return priv->switch_init(priv); |
| 1027 | } |
| 1028 | |
| 1029 | static int mtk_eth_remove(struct udevice *dev) |
| 1030 | { |
| 1031 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 1032 | |
| 1033 | /* MDIO unregister */ |
| 1034 | mdio_unregister(priv->mdio_bus); |
| 1035 | mdio_free(priv->mdio_bus); |
| 1036 | |
| 1037 | /* Stop possibly started DMA */ |
| 1038 | mtk_eth_stop(dev); |
| 1039 | |
| 1040 | return 0; |
| 1041 | } |
| 1042 | |
| 1043 | static int mtk_eth_ofdata_to_platdata(struct udevice *dev) |
| 1044 | { |
| 1045 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 1046 | struct mtk_eth_priv *priv = dev_get_priv(dev); |
| 1047 | struct ofnode_phandle_args args; |
| 1048 | struct regmap *regmap; |
| 1049 | const char *str; |
| 1050 | ofnode subnode; |
| 1051 | int ret; |
| 1052 | |
| 1053 | priv->soc = dev_get_driver_data(dev); |
| 1054 | |
| 1055 | pdata->iobase = devfdt_get_addr(dev); |
| 1056 | |
| 1057 | /* get corresponding ethsys phandle */ |
| 1058 | ret = dev_read_phandle_with_args(dev, "mediatek,ethsys", NULL, 0, 0, |
| 1059 | &args); |
| 1060 | if (ret) |
| 1061 | return ret; |
| 1062 | |
| 1063 | regmap = syscon_node_to_regmap(args.node); |
| 1064 | if (IS_ERR(regmap)) |
| 1065 | return PTR_ERR(regmap); |
| 1066 | |
| 1067 | priv->ethsys_base = regmap_get_range(regmap, 0); |
| 1068 | if (!priv->ethsys_base) { |
| 1069 | dev_err(dev, "Unable to find ethsys\n"); |
| 1070 | return -ENODEV; |
| 1071 | } |
| 1072 | |
| 1073 | /* Reset controllers */ |
| 1074 | ret = reset_get_by_name(dev, "fe", &priv->rst_fe); |
| 1075 | if (ret) { |
| 1076 | printf("error: Unable to get reset ctrl for frame engine\n"); |
| 1077 | return ret; |
| 1078 | } |
| 1079 | |
| 1080 | priv->gmac_id = dev_read_u32_default(dev, "mediatek,gmac-id", 0); |
| 1081 | |
| 1082 | /* Interface mode is required */ |
| 1083 | str = dev_read_string(dev, "phy-mode"); |
| 1084 | if (str) { |
| 1085 | pdata->phy_interface = phy_get_interface_by_name(str); |
| 1086 | priv->phy_interface = pdata->phy_interface; |
| 1087 | } else { |
| 1088 | printf("error: phy-mode is not set\n"); |
| 1089 | return -EINVAL; |
| 1090 | } |
| 1091 | |
| 1092 | /* Force mode or autoneg */ |
| 1093 | subnode = ofnode_find_subnode(dev_ofnode(dev), "fixed-link"); |
| 1094 | if (ofnode_valid(subnode)) { |
| 1095 | priv->force_mode = 1; |
| 1096 | priv->speed = ofnode_read_u32_default(subnode, "speed", 0); |
| 1097 | priv->duplex = ofnode_read_bool(subnode, "full-duplex"); |
| 1098 | |
| 1099 | if (priv->speed != SPEED_10 && priv->speed != SPEED_100 && |
| 1100 | priv->speed != SPEED_1000) { |
| 1101 | printf("error: no valid speed set in fixed-link\n"); |
| 1102 | return -EINVAL; |
| 1103 | } |
| 1104 | } |
| 1105 | |
| 1106 | /* check for switch first, otherwise phy will be used */ |
| 1107 | priv->sw = SW_NONE; |
| 1108 | priv->switch_init = NULL; |
| 1109 | str = dev_read_string(dev, "mediatek,switch"); |
| 1110 | |
| 1111 | if (str) { |
| 1112 | if (!strcmp(str, "mt7530")) { |
| 1113 | priv->sw = SW_MT7530; |
| 1114 | priv->switch_init = mt7530_setup; |
| 1115 | priv->mt7530_smi_addr = MT7530_DFL_SMI_ADDR; |
| 1116 | } else { |
| 1117 | printf("error: unsupported switch\n"); |
| 1118 | return -EINVAL; |
| 1119 | } |
| 1120 | |
| 1121 | priv->mcm = dev_read_bool(dev, "mediatek,mcm"); |
| 1122 | if (priv->mcm) { |
| 1123 | ret = reset_get_by_name(dev, "mcm", &priv->rst_mcm); |
| 1124 | if (ret) { |
| 1125 | printf("error: no reset ctrl for mcm\n"); |
| 1126 | return ret; |
| 1127 | } |
| 1128 | } else { |
| 1129 | gpio_request_by_name(dev, "reset-gpios", 0, |
| 1130 | &priv->rst_gpio, GPIOD_IS_OUT); |
| 1131 | } |
| 1132 | } else { |
Weijie Gao | ebb97ea | 2019-04-28 15:08:57 +0800 | [diff] [blame] | 1133 | ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, |
| 1134 | 0, &args); |
| 1135 | if (ret) { |
Weijie Gao | 23f1716 | 2018-12-20 16:12:53 +0800 | [diff] [blame] | 1136 | printf("error: phy-handle is not specified\n"); |
| 1137 | return ret; |
| 1138 | } |
| 1139 | |
Weijie Gao | ebb97ea | 2019-04-28 15:08:57 +0800 | [diff] [blame] | 1140 | priv->phy_addr = ofnode_read_s32_default(args.node, "reg", -1); |
Weijie Gao | 23f1716 | 2018-12-20 16:12:53 +0800 | [diff] [blame] | 1141 | if (priv->phy_addr < 0) { |
| 1142 | printf("error: phy address is not specified\n"); |
| 1143 | return ret; |
| 1144 | } |
| 1145 | } |
| 1146 | |
| 1147 | return 0; |
| 1148 | } |
| 1149 | |
| 1150 | static const struct udevice_id mtk_eth_ids[] = { |
| 1151 | { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 }, |
| 1152 | { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 }, |
| 1153 | {} |
| 1154 | }; |
| 1155 | |
| 1156 | static const struct eth_ops mtk_eth_ops = { |
| 1157 | .start = mtk_eth_start, |
| 1158 | .stop = mtk_eth_stop, |
| 1159 | .send = mtk_eth_send, |
| 1160 | .recv = mtk_eth_recv, |
| 1161 | .free_pkt = mtk_eth_free_pkt, |
| 1162 | .write_hwaddr = mtk_eth_write_hwaddr, |
| 1163 | }; |
| 1164 | |
| 1165 | U_BOOT_DRIVER(mtk_eth) = { |
| 1166 | .name = "mtk-eth", |
| 1167 | .id = UCLASS_ETH, |
| 1168 | .of_match = mtk_eth_ids, |
| 1169 | .ofdata_to_platdata = mtk_eth_ofdata_to_platdata, |
| 1170 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), |
| 1171 | .probe = mtk_eth_probe, |
| 1172 | .remove = mtk_eth_remove, |
| 1173 | .ops = &mtk_eth_ops, |
| 1174 | .priv_auto_alloc_size = sizeof(struct mtk_eth_priv), |
| 1175 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
| 1176 | }; |