blob: 312b0eb91f7bf1e637d168dc012842f6f0d44867 [file] [log] [blame]
Shengzhou Liu8d67c362014-03-05 15:04:48 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T2080 RDB/PCIe board configuration file
9 */
10
11#ifndef __T2080RDB_H
12#define __T2080RDB_H
13
Shengzhou Liufb536872014-07-23 15:54:16 +080014#define CONFIG_DISPLAY_BOARDINFO
Shengzhou Liu8d67c362014-03-05 15:04:48 +080015#define CONFIG_T2080RDB
16#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17#define CONFIG_MMC
Shengzhou Liu8d67c362014-03-05 15:04:48 +080018#define CONFIG_USB_EHCI
19#define CONFIG_FSL_SATA_V2
20
21/* High Level Configuration Options */
22#define CONFIG_PHYS_64BIT
23#define CONFIG_BOOKE
24#define CONFIG_E500 /* BOOKE e500 family */
25#define CONFIG_E500MC /* BOOKE e500mc family */
26#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27#define CONFIG_MP /* support multiple processors */
28#define CONFIG_ENABLE_36BIT_PHYS
29
30#ifdef CONFIG_PHYS_64BIT
31#define CONFIG_ADDR_MAP 1
32#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
33#endif
34
35#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
36#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
37#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053038#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Shengzhou Liu8d67c362014-03-05 15:04:48 +080039#define CONFIG_FSL_LAW /* Use common FSL init code */
40#define CONFIG_ENV_OVERWRITE
41
42#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090043#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
44#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080045
Shengzhou Liu4d666682014-04-18 16:43:40 +080046#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
47#define CONFIG_SPL_ENV_SUPPORT
48#define CONFIG_SPL_SERIAL_SUPPORT
49#define CONFIG_SPL_FLUSH_IMAGE
50#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
51#define CONFIG_SPL_LIBGENERIC_SUPPORT
52#define CONFIG_SPL_LIBCOMMON_SUPPORT
53#define CONFIG_SPL_I2C_SUPPORT
54#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
55#define CONFIG_FSL_LAW /* Use common FSL init code */
56#define CONFIG_SYS_TEXT_BASE 0x00201000
57#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
58#define CONFIG_SPL_PAD_TO 0x40000
59#define CONFIG_SPL_MAX_SIZE 0x28000
60#define RESET_VECTOR_OFFSET 0x27FFC
61#define BOOT_PAGE_OFFSET 0x27000
62#ifdef CONFIG_SPL_BUILD
63#define CONFIG_SPL_SKIP_RELOCATE
64#define CONFIG_SPL_COMMON_INIT_DDR
65#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
66#define CONFIG_SYS_NO_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +080067#endif
68
Shengzhou Liu4d666682014-04-18 16:43:40 +080069#ifdef CONFIG_NAND
70#define CONFIG_SPL_NAND_SUPPORT
71#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
72#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
73#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
74#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
75#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
76#define CONFIG_SPL_NAND_BOOT
77#endif
78
79#ifdef CONFIG_SPIFLASH
80#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
81#define CONFIG_SPL_SPI_SUPPORT
82#define CONFIG_SPL_SPI_FLASH_SUPPORT
83#define CONFIG_SPL_SPI_FLASH_MINIMAL
84#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
85#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
86#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
87#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
88#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
89#ifndef CONFIG_SPL_BUILD
90#define CONFIG_SYS_MPC85XX_NO_RESETVEC
91#endif
92#define CONFIG_SPL_SPI_BOOT
93#endif
94
95#ifdef CONFIG_SDCARD
96#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
97#define CONFIG_SPL_MMC_SUPPORT
98#define CONFIG_SPL_MMC_MINIMAL
99#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
100#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
101#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
102#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
103#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
104#ifndef CONFIG_SPL_BUILD
105#define CONFIG_SYS_MPC85XX_NO_RESETVEC
106#endif
107#define CONFIG_SPL_MMC_BOOT
108#endif
109
110#endif /* CONFIG_RAMBOOT_PBL */
111
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800112#define CONFIG_SRIO_PCIE_BOOT_MASTER
113#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
114/* Set 1M boot space */
115#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
116#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
117 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
118#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
119#define CONFIG_SYS_NO_FLASH
120#endif
121
122#ifndef CONFIG_SYS_TEXT_BASE
123#define CONFIG_SYS_TEXT_BASE 0xeff40000
124#endif
125
126#ifndef CONFIG_RESET_VECTOR_ADDRESS
127#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
128#endif
129
130/*
131 * These can be toggled for performance analysis, otherwise use default.
132 */
133#define CONFIG_SYS_CACHE_STASHING
134#define CONFIG_BTB /* toggle branch predition */
135#define CONFIG_DDR_ECC
136#ifdef CONFIG_DDR_ECC
137#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
138#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
139#endif
140
Shengzhou Liu49132292015-03-27 15:53:14 +0800141#define CONFIG_CMD_MEMTEST
142#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
143#define CONFIG_SYS_MEMTEST_END 0x00400000
144#define CONFIG_SYS_ALT_MEMTEST
145
Shengzhou Liu4d666682014-04-18 16:43:40 +0800146#ifndef CONFIG_SYS_NO_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800147#define CONFIG_FLASH_CFI_DRIVER
148#define CONFIG_SYS_FLASH_CFI
149#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
150#endif
151
152#if defined(CONFIG_SPIFLASH)
153#define CONFIG_SYS_EXTRA_ENV_RELOC
154#define CONFIG_ENV_IS_IN_SPI_FLASH
155#define CONFIG_ENV_SPI_BUS 0
156#define CONFIG_ENV_SPI_CS 0
157#define CONFIG_ENV_SPI_MAX_HZ 10000000
158#define CONFIG_ENV_SPI_MODE 0
159#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
160#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
161#define CONFIG_ENV_SECT_SIZE 0x10000
162#elif defined(CONFIG_SDCARD)
163#define CONFIG_SYS_EXTRA_ENV_RELOC
164#define CONFIG_ENV_IS_IN_MMC
165#define CONFIG_SYS_MMC_ENV_DEV 0
166#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liu4d666682014-04-18 16:43:40 +0800167#define CONFIG_ENV_OFFSET (512 * 0x800)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800168#elif defined(CONFIG_NAND)
169#define CONFIG_SYS_EXTRA_ENV_RELOC
170#define CONFIG_ENV_IS_IN_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +0800171#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800172#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
173#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
174#define CONFIG_ENV_IS_IN_REMOTE
175#define CONFIG_ENV_ADDR 0xffe20000
176#define CONFIG_ENV_SIZE 0x2000
177#elif defined(CONFIG_ENV_IS_NOWHERE)
178#define CONFIG_ENV_SIZE 0x2000
179#else
180#define CONFIG_ENV_IS_IN_FLASH
181#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
182#define CONFIG_ENV_SIZE 0x2000
183#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
184#endif
185
186#ifndef __ASSEMBLY__
187unsigned long get_board_sys_clk(void);
188unsigned long get_board_ddr_clk(void);
189#endif
190
191#define CONFIG_SYS_CLK_FREQ 66660000
192#define CONFIG_DDR_CLK_FREQ 133330000
193
194/*
195 * Config the L3 Cache as L3 SRAM
196 */
Shengzhou Liu4d666682014-04-18 16:43:40 +0800197#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
198#define CONFIG_SYS_L3_SIZE (512 << 10)
199#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
200#ifdef CONFIG_RAMBOOT_PBL
201#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
202#endif
203#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
204#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
205#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
206#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800207
208#define CONFIG_SYS_DCSRBAR 0xf0000000
209#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
210
211/* EEPROM */
212#define CONFIG_ID_EEPROM
213#define CONFIG_SYS_I2C_EEPROM_NXID
214#define CONFIG_SYS_EEPROM_BUS_NUM 0
215#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
Shengzhou Liuef531c72014-04-18 16:43:41 +0800216#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800217
218/*
219 * DDR Setup
220 */
221#define CONFIG_VERY_BIG_RAM
222#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
223#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
224#define CONFIG_DIMM_SLOTS_PER_CTLR 1
225#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
226#define CONFIG_DDR_SPD
227#define CONFIG_SYS_FSL_DDR3
228#undef CONFIG_FSL_DDR_INTERACTIVE
229#define CONFIG_SYS_SPD_BUS_NUM 0
230#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
231#define SPD_EEPROM_ADDRESS1 0x51
232#define SPD_EEPROM_ADDRESS2 0x52
233#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
234#define CTRL_INTLV_PREFERED cacheline
235
236/*
237 * IFC Definitions
238 */
239#define CONFIG_SYS_FLASH_BASE 0xe8000000
240#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
241#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
242#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
243 CSPR_PORT_SIZE_16 | \
244 CSPR_MSEL_NOR | \
245 CSPR_V)
246#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
247
248/* NOR Flash Timing Params */
249#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
250
251#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
252 FTIM0_NOR_TEADC(0x5) | \
253 FTIM0_NOR_TEAHC(0x5))
254#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
255 FTIM1_NOR_TRAD_NOR(0x1A) |\
256 FTIM1_NOR_TSEQRAD_NOR(0x13))
257#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
258 FTIM2_NOR_TCH(0x4) | \
259 FTIM2_NOR_TWPH(0x0E) | \
260 FTIM2_NOR_TWP(0x1c))
261#define CONFIG_SYS_NOR_FTIM3 0x0
262
263#define CONFIG_SYS_FLASH_QUIET_TEST
264#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
265
266#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
267#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
268#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
269#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
270#define CONFIG_SYS_FLASH_EMPTY_INFO
271#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
272
273/* CPLD on IFC */
274#define CONFIG_SYS_CPLD_BASE 0xffdf0000
275#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
276#define CONFIG_SYS_CSPR2_EXT (0xf)
277#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
278 | CSPR_PORT_SIZE_8 \
279 | CSPR_MSEL_GPCM \
280 | CSPR_V)
281#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
282#define CONFIG_SYS_CSOR2 0x0
283
284/* CPLD Timing parameters for IFC CS2 */
285#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
286 FTIM0_GPCM_TEADC(0x0e) | \
287 FTIM0_GPCM_TEAHC(0x0e))
288#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
289 FTIM1_GPCM_TRAD(0x1f))
290#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800291 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800292 FTIM2_GPCM_TWP(0x1f))
293#define CONFIG_SYS_CS2_FTIM3 0x0
294
295/* NAND Flash on IFC */
296#define CONFIG_NAND_FSL_IFC
297#define CONFIG_SYS_NAND_BASE 0xff800000
298#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
299
300#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
301#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
302 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
303 | CSPR_MSEL_NAND /* MSEL = NAND */ \
304 | CSPR_V)
305#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
306
307#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
308 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
309 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
310 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
311 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
312 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
313 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
314
315#define CONFIG_SYS_NAND_ONFI_DETECTION
316
317/* ONFI NAND Flash mode0 Timing Params */
318#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
319 FTIM0_NAND_TWP(0x18) | \
320 FTIM0_NAND_TWCHT(0x07) | \
321 FTIM0_NAND_TWH(0x0a))
322#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
323 FTIM1_NAND_TWBE(0x39) | \
324 FTIM1_NAND_TRR(0x0e) | \
325 FTIM1_NAND_TRP(0x18))
326#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
327 FTIM2_NAND_TREH(0x0a) | \
328 FTIM2_NAND_TWHRE(0x1e))
329#define CONFIG_SYS_NAND_FTIM3 0x0
330
331#define CONFIG_SYS_NAND_DDR_LAW 11
332#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
333#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800334#define CONFIG_CMD_NAND
335#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
336
337#if defined(CONFIG_NAND)
338#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
339#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
340#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
341#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
342#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
343#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
344#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
345#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
346#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
347#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
348#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
349#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
350#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
351#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
352#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
353#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
354#else
355#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
356#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
357#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
358#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
359#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
360#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
361#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
362#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
363#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
364#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
365#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
366#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
367#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
368#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
369#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
370#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
371#endif
372
373#if defined(CONFIG_RAMBOOT_PBL)
374#define CONFIG_SYS_RAMBOOT
375#endif
376
Shengzhou Liu4d666682014-04-18 16:43:40 +0800377#ifdef CONFIG_SPL_BUILD
378#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
379#else
380#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
381#endif
382
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800383#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
384#define CONFIG_MISC_INIT_R
385#define CONFIG_HWCONFIG
386
387/* define to use L1 as initial stack */
388#define CONFIG_L1_INIT_RAM
389#define CONFIG_SYS_INIT_RAM_LOCK
390#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
391#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700392#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800393/* The assembler doesn't like typecast */
394#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
395 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
396 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
397#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
398#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
399 GENERATED_GBL_DATA_SIZE)
400#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530401#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800402#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
403
404/*
405 * Serial Port
406 */
407#define CONFIG_CONS_INDEX 1
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800408#define CONFIG_SYS_NS16550_SERIAL
409#define CONFIG_SYS_NS16550_REG_SIZE 1
410#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
411#define CONFIG_SYS_BAUDRATE_TABLE \
412 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
413#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
414#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
415#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
416#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
417
418/* Use the HUSH parser */
419#define CONFIG_SYS_HUSH_PARSER
420#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
421
422/* pass open firmware flat tree */
423#define CONFIG_OF_LIBFDT
424#define CONFIG_OF_BOARD_SETUP
425#define CONFIG_OF_STDOUT_VIA_ALIAS
426
427/* new uImage format support */
428#define CONFIG_FIT
429#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
430
431/*
432 * I2C
433 */
434#define CONFIG_SYS_I2C
435#define CONFIG_SYS_I2C_FSL
436#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
437#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
438#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
439#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
440#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
441#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
442#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
443#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
444#define CONFIG_SYS_FSL_I2C_SPEED 100000
445#define CONFIG_SYS_FSL_I2C2_SPEED 100000
446#define CONFIG_SYS_FSL_I2C3_SPEED 100000
447#define CONFIG_SYS_FSL_I2C4_SPEED 100000
448#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
449#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
450#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
451#define I2C_MUX_CH_DEFAULT 0x8
452
Ying Zhange5abb922015-03-10 14:21:36 +0800453#define I2C_MUX_CH_VOL_MONITOR 0xa
454
455#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
456#ifndef CONFIG_SPL_BUILD
457#define CONFIG_VID
458#endif
459#define CONFIG_VOL_MONITOR_IR36021_SET
460#define CONFIG_VOL_MONITOR_IR36021_READ
461/* The lowest and highest voltage allowed for T208xRDB */
462#define VDD_MV_MIN 819
463#define VDD_MV_MAX 1212
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800464
465/*
466 * RapidIO
467 */
468#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
469#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
470#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
471#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
472#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
473#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
474/*
475 * for slave u-boot IMAGE instored in master memory space,
476 * PHYS must be aligned based on the SIZE
477 */
Liu Gange4911812014-05-15 14:30:34 +0800478#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
479#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
480#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
481#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800482/*
483 * for slave UCODE and ENV instored in master memory space,
484 * PHYS must be aligned based on the SIZE
485 */
Liu Gange4911812014-05-15 14:30:34 +0800486#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800487#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
488#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
489
490/* slave core release by master*/
491#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
492#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
493
494/*
495 * SRIO_PCIE_BOOT - SLAVE
496 */
497#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
498#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
499#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
500 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
501#endif
502
503/*
504 * eSPI - Enhanced SPI
505 */
506#ifdef CONFIG_SPI_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800507#define CONFIG_SPI_FLASH_BAR
508#define CONFIG_CMD_SF
509#define CONFIG_SF_DEFAULT_SPEED 10000000
510#define CONFIG_SF_DEFAULT_MODE 0
511#endif
512
513/*
514 * General PCI
515 * Memory space is mapped 1-1, but I/O space must start from 0.
516 */
517#define CONFIG_PCI /* Enable PCI/PCIE */
518#define CONFIG_PCIE1 /* PCIE controler 1 */
519#define CONFIG_PCIE2 /* PCIE controler 2 */
520#define CONFIG_PCIE3 /* PCIE controler 3 */
521#define CONFIG_PCIE4 /* PCIE controler 4 */
522#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
523#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
524/* controller 1, direct to uli, tgtid 3, Base address 20000 */
525#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
526#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
527#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
528#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
529#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
530#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
531#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
532#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
533
534/* controller 2, Slot 2, tgtid 2, Base address 201000 */
535#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
536#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
537#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
538#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
539#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
540#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
541#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
542#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
543
544/* controller 3, Slot 1, tgtid 1, Base address 202000 */
545#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
546#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
547#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
548#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
549#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
550#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
551#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
552#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
553
554/* controller 4, Base address 203000 */
555#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
556#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
557#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
558#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
559#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
560#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
561#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
562
563#ifdef CONFIG_PCI
564#define CONFIG_PCI_INDIRECT_BRIDGE
565#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800566#define CONFIG_PCI_PNP /* do pci plug-and-play */
567#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
568#define CONFIG_DOS_PARTITION
569#endif
570
571/* Qman/Bman */
572#ifndef CONFIG_NOBQFMAN
573#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
574#define CONFIG_SYS_BMAN_NUM_PORTALS 18
575#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
576#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
577#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500578#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
579#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
580#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
581#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
582#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
583 CONFIG_SYS_BMAN_CENA_SIZE)
584#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
585#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800586#define CONFIG_SYS_QMAN_NUM_PORTALS 18
587#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
588#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
589#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500590#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
591#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
592#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
593#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
594#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
595 CONFIG_SYS_QMAN_CENA_SIZE)
596#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
597#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800598
599#define CONFIG_SYS_DPAA_FMAN
600#define CONFIG_SYS_DPAA_PME
601#define CONFIG_SYS_PMAN
602#define CONFIG_SYS_DPAA_DCE
603#define CONFIG_SYS_DPAA_RMAN /* RMan */
604#define CONFIG_SYS_INTERLAKEN
605
606/* Default address of microcode for the Linux Fman driver */
607#if defined(CONFIG_SPIFLASH)
608/*
609 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
610 * env, so we got 0x110000.
611 */
612#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Shengzhou Liuef531c72014-04-18 16:43:41 +0800613#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
614#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800615#define CONFIG_CORTINA_FW_ADDR 0x120000
616
617#elif defined(CONFIG_SDCARD)
618/*
619 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liu4d666682014-04-18 16:43:40 +0800620 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
621 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800622 */
623#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shengzhou Liuef531c72014-04-18 16:43:41 +0800624#define CONFIG_SYS_CORTINA_FW_IN_MMC
Shengzhou Liu4d666682014-04-18 16:43:40 +0800625#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
626#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800627
628#elif defined(CONFIG_NAND)
629#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liuef531c72014-04-18 16:43:41 +0800630#define CONFIG_SYS_CORTINA_FW_IN_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +0800631#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
632#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800633#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
634/*
635 * Slave has no ucode locally, it can fetch this from remote. When implementing
636 * in two corenet boards, slave's ucode could be stored in master's memory
637 * space, the address can be mapped from slave TLB->slave LAW->
638 * slave SRIO or PCIE outbound window->master inbound window->
639 * master LAW->the ucode address in master's memory space.
640 */
641#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Shengzhou Liuef531c72014-04-18 16:43:41 +0800642#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
643#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800644#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
645#else
646#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Shengzhou Liuef531c72014-04-18 16:43:41 +0800647#define CONFIG_SYS_CORTINA_FW_IN_NOR
648#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800649#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
650#endif
651#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
652#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
653#endif /* CONFIG_NOBQFMAN */
654
655#ifdef CONFIG_SYS_DPAA_FMAN
656#define CONFIG_FMAN_ENET
657#define CONFIG_PHYLIB_10G
Shengzhou Liu747aeda2015-04-08 11:12:15 +0800658#define CONFIG_PHY_AQUANTIA
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800659#define CONFIG_PHY_CORTINA
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800660#define CONFIG_PHY_REALTEK
661#define CONFIG_CORTINA_FW_LENGTH 0x40000
662#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
663#define RGMII_PHY2_ADDR 0x02
664#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
665#define CORTINA_PHY_ADDR2 0x0d
666#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
667#define FM1_10GEC4_PHY_ADDR 0x01
668#endif
669
670
671#ifdef CONFIG_FMAN_ENET
672#define CONFIG_MII /* MII PHY management */
673#define CONFIG_ETHPRIME "FM1@DTSEC3"
674#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
675#endif
676
677/*
678 * SATA
679 */
680#ifdef CONFIG_FSL_SATA_V2
681#define CONFIG_LIBATA
682#define CONFIG_FSL_SATA
683#define CONFIG_SYS_SATA_MAX_DEVICE 2
684#define CONFIG_SATA1
685#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
686#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
687#define CONFIG_SATA2
688#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
689#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
690#define CONFIG_LBA48
691#define CONFIG_CMD_SATA
692#define CONFIG_DOS_PARTITION
693#define CONFIG_CMD_EXT2
694#endif
695
696/*
697 * USB
698 */
699#ifdef CONFIG_USB_EHCI
700#define CONFIG_CMD_USB
701#define CONFIG_USB_STORAGE
702#define CONFIG_USB_EHCI_FSL
703#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
704#define CONFIG_CMD_EXT2
705#define CONFIG_HAS_FSL_DR_USB
706#endif
707
708/*
709 * SDHC
710 */
711#ifdef CONFIG_MMC
712#define CONFIG_CMD_MMC
713#define CONFIG_FSL_ESDHC
714#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
715#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
716#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
717#define CONFIG_GENERIC_MMC
718#define CONFIG_CMD_EXT2
719#define CONFIG_CMD_FAT
720#define CONFIG_DOS_PARTITION
721#endif
722
723/*
Shengzhou Liu4feac1c2014-04-02 14:28:35 +0800724 * Dynamic MTD Partition support with mtdparts
725 */
726#ifndef CONFIG_SYS_NO_FLASH
727#define CONFIG_MTD_DEVICE
728#define CONFIG_MTD_PARTITIONS
729#define CONFIG_CMD_MTDPARTS
730#define CONFIG_FLASH_CFI_MTD
731#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
732 "spi0=spife110000.1"
733#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
734 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
735 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
736 "1m(uboot),5m(kernel),128k(dtb),-(user)"
737#endif
738
739/*
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800740 * Environment
741 */
742
743/*
744 * Command line configuration.
745 */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800746#define CONFIG_CMD_DHCP
Shengzhou Liuc665c472014-04-24 11:10:09 +0800747#define CONFIG_CMD_ERRATA
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800748#define CONFIG_CMD_MII
749#define CONFIG_CMD_I2C
750#define CONFIG_CMD_PING
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800751#define CONFIG_CMD_REGINFO
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800752
753#ifdef CONFIG_PCI
754#define CONFIG_CMD_PCI
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800755#endif
756
Ruchika Gupta737537e2014-10-15 11:35:31 +0530757/* Hash command with SHA acceleration supported in hardware */
758#ifdef CONFIG_FSL_CAAM
759#define CONFIG_CMD_HASH
760#define CONFIG_SHA_HW_ACCEL
761#endif
762
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800763/*
764 * Miscellaneous configurable options
765 */
766#define CONFIG_SYS_LONGHELP /* undef to save memory */
767#define CONFIG_CMDLINE_EDITING /* Command-line editing */
768#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
769#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800770#ifdef CONFIG_CMD_KGDB
771#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
772#else
773#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
774#endif
775#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
776#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
777#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800778
779/*
780 * For booting Linux, the board info and command line data
781 * have to be in the first 64 MB of memory, since this is
782 * the maximum mapped by the Linux kernel during initialization.
783 */
784#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
785#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
786
787#ifdef CONFIG_CMD_KGDB
788#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
789#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
790#endif
791
792/*
793 * Environment Configuration
794 */
795#define CONFIG_ROOTPATH "/opt/nfsroot"
796#define CONFIG_BOOTFILE "uImage"
797#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
798
799/* default location for tftp and bootm */
800#define CONFIG_LOADADDR 1000000
801#define CONFIG_BAUDRATE 115200
802#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
803#define __USB_PHY_TYPE utmi
804
805#define CONFIG_EXTRA_ENV_SETTINGS \
806 "hwconfig=fsl_ddr:" \
807 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
808 "bank_intlv=auto;" \
809 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
810 "netdev=eth0\0" \
811 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
812 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
813 "tftpflash=tftpboot $loadaddr $uboot && " \
814 "protect off $ubootaddr +$filesize && " \
815 "erase $ubootaddr +$filesize && " \
816 "cp.b $loadaddr $ubootaddr $filesize && " \
817 "protect on $ubootaddr +$filesize && " \
818 "cmp.b $loadaddr $ubootaddr $filesize\0" \
819 "consoledev=ttyS0\0" \
820 "ramdiskaddr=2000000\0" \
821 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
822 "fdtaddr=c00000\0" \
823 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500824 "bdev=sda3\0"
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800825
826/*
827 * For emulation this causes u-boot to jump to the start of the
828 * proof point app code automatically
829 */
830#define CONFIG_PROOF_POINTS \
831 "setenv bootargs root=/dev/$bdev rw " \
832 "console=$consoledev,$baudrate $othbootargs;" \
833 "cpu 1 release 0x29000000 - - -;" \
834 "cpu 2 release 0x29000000 - - -;" \
835 "cpu 3 release 0x29000000 - - -;" \
836 "cpu 4 release 0x29000000 - - -;" \
837 "cpu 5 release 0x29000000 - - -;" \
838 "cpu 6 release 0x29000000 - - -;" \
839 "cpu 7 release 0x29000000 - - -;" \
840 "go 0x29000000"
841
842#define CONFIG_HVBOOT \
843 "setenv bootargs config-addr=0x60000000; " \
844 "bootm 0x01000000 - 0x00f00000"
845
846#define CONFIG_ALU \
847 "setenv bootargs root=/dev/$bdev rw " \
848 "console=$consoledev,$baudrate $othbootargs;" \
849 "cpu 1 release 0x01000000 - - -;" \
850 "cpu 2 release 0x01000000 - - -;" \
851 "cpu 3 release 0x01000000 - - -;" \
852 "cpu 4 release 0x01000000 - - -;" \
853 "cpu 5 release 0x01000000 - - -;" \
854 "cpu 6 release 0x01000000 - - -;" \
855 "cpu 7 release 0x01000000 - - -;" \
856 "go 0x01000000"
857
858#define CONFIG_LINUX \
859 "setenv bootargs root=/dev/ram rw " \
860 "console=$consoledev,$baudrate $othbootargs;" \
861 "setenv ramdiskaddr 0x02000000;" \
862 "setenv fdtaddr 0x00c00000;" \
863 "setenv loadaddr 0x1000000;" \
864 "bootm $loadaddr $ramdiskaddr $fdtaddr"
865
866#define CONFIG_HDBOOT \
867 "setenv bootargs root=/dev/$bdev rw " \
868 "console=$consoledev,$baudrate $othbootargs;" \
869 "tftp $loadaddr $bootfile;" \
870 "tftp $fdtaddr $fdtfile;" \
871 "bootm $loadaddr - $fdtaddr"
872
873#define CONFIG_NFSBOOTCOMMAND \
874 "setenv bootargs root=/dev/nfs rw " \
875 "nfsroot=$serverip:$rootpath " \
876 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
877 "console=$consoledev,$baudrate $othbootargs;" \
878 "tftp $loadaddr $bootfile;" \
879 "tftp $fdtaddr $fdtfile;" \
880 "bootm $loadaddr - $fdtaddr"
881
882#define CONFIG_RAMBOOTCOMMAND \
883 "setenv bootargs root=/dev/ram rw " \
884 "console=$consoledev,$baudrate $othbootargs;" \
885 "tftp $ramdiskaddr $ramdiskfile;" \
886 "tftp $loadaddr $bootfile;" \
887 "tftp $fdtaddr $fdtfile;" \
888 "bootm $loadaddr $ramdiskaddr $fdtaddr"
889
890#define CONFIG_BOOTCOMMAND CONFIG_LINUX
891
892#ifdef CONFIG_SECURE_BOOT
893#include <asm/fsl_secure_boot.h>
Ruchika Gupta789490b2014-10-07 15:48:46 +0530894#define CONFIG_CMD_BLOB
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800895#undef CONFIG_CMD_USB
896#endif
897
898#endif /* __T2080RDB_H */