Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 1 | .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
| 2 | .. sectionauthor:: Bryan Brattlof <bb@ti.com> |
| 3 | |
| 4 | K3 Generation |
| 5 | ============= |
| 6 | |
| 7 | Summary |
| 8 | ------- |
| 9 | |
| 10 | Texas Instrument's K3 family of SoCs utilize a heterogeneous multicore |
| 11 | and highly integrated device architecture targeted to maximize |
| 12 | performance and power efficiency for a wide range of industrial, |
| 13 | automotive and other broad market segments. |
| 14 | |
| 15 | Typically the processing cores and the peripherals for these devices are |
| 16 | partitioned into three functional domains to provide ultra-low power |
| 17 | modes as well as accommodating application and industrial safety systems |
| 18 | on the same SoC. These functional domains are typically called the: |
| 19 | |
| 20 | * Wakeup (WKUP) domain |
| 21 | * Micro-controller (MCU) domain |
| 22 | * Main domain |
| 23 | |
| 24 | For a more detailed view of what peripherals are attached to each |
| 25 | domain, consult the device specific documentation. |
| 26 | |
| 27 | K3 Based SoCs |
| 28 | ------------- |
| 29 | |
| 30 | .. toctree:: |
| 31 | :maxdepth: 1 |
| 32 | |
| 33 | j721e_evm |
Udit Kumar | db7af51 | 2023-05-11 14:47:48 +0530 | [diff] [blame] | 34 | j7200_evm |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 35 | am62x_sk |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 36 | am65x_evm |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 37 | |
| 38 | Boot Flow Overview |
| 39 | ------------------ |
| 40 | |
| 41 | For all K3 SoCs the first core started will be inside the Security |
| 42 | Management Subsystem (SMS) which will secure the device and start a core |
| 43 | in the wakeup domain to run the ROM code. ROM will then initialize the |
| 44 | boot media needed to load the binaries packaged inside `tiboot3.bin`, |
| 45 | including a 32bit U-Boot SPL, (called the wakup SPL) that ROM will jump |
| 46 | to after it has finished loading everything into internal SRAM. |
| 47 | |
| 48 | .. code-block:: text |
| 49 | |
| 50 | | WKUP Domain |
| 51 | ROM -> WKUP SPL -> |
| 52 | |
| 53 | The wakeup SPL, running on a wakeup domain core, will initialize DDR and |
| 54 | any peripherals needed load the larger binaries inside the `tispl.bin` |
| 55 | into DDR. Once loaded the wakeup SPL will start one of the 'big' |
| 56 | application cores inside the main domain to initialize the main domain, |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 57 | starting with Trusted Firmware-A (TF-A), before moving on to start |
| 58 | OP-TEE and the main domain's U-Boot SPL. |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 59 | |
| 60 | .. code-block:: text |
| 61 | |
| 62 | | WKUP Domain | Main Domain -> |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 63 | ROM -> WKUP SPL -> TF-A -> OP-TEE -> Main SPL |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 64 | |
| 65 | The main domain's SPL, running on a 64bit application core, has |
| 66 | virtually unlimited space (billions of bytes now that DDR is working) to |
| 67 | initialize even more peripherals needed to load in the `u-boot.img` |
| 68 | which loads more firmware into the micro-controller & wakeup domains and |
| 69 | finally prepare the main domain to run Linux. |
| 70 | |
| 71 | .. code-block:: text |
| 72 | |
| 73 | | WKUP Domain | Main Domain -> |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 74 | ROM -> WKUP SPL -> TF-A -> OP-TEE -> Main SPL -> UBoot -> Linux |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 75 | |
| 76 | This is the typical boot flow for all K3 based SoCs, however this flow |
| 77 | offers quite a lot in the terms of flexibility, especially on High |
| 78 | Security (HS) SoCs. |
| 79 | |
| 80 | Boot Flow Variations |
| 81 | ^^^^^^^^^^^^^^^^^^^^ |
| 82 | |
| 83 | All K3 SoCs will generally use the above boot flow with two main |
| 84 | differences depending on the capabilities of the boot ROM and the number |
| 85 | of cores inside the device. These differences split the bootflow into |
| 86 | essentially 4 unique but very similar flows: |
| 87 | |
| 88 | * Split binary with a combined firmware: (eg: AM65) |
| 89 | * Combined binary with a combined firmware: (eg: AM64) |
| 90 | * Split binary with a split firmware: (eg: J721E) |
| 91 | * Combined binary with a split firmware: (eg: AM62) |
| 92 | |
| 93 | For devices that utilize the split binary approach, ROM is not capable |
| 94 | of loading the firmware into the SoC requiring the wakeup domain's |
| 95 | U-Boot SPL to load the firmware. |
| 96 | |
| 97 | Devices with a split firmware will have two firmwares loaded into the |
| 98 | device at different times during the bootup process. TI's Foundational |
| 99 | Security (TIFS), needed to operate the Security Management Subsystem, |
| 100 | will either be loaded by ROM or the WKUP U-Boot SPL, then once the |
| 101 | wakeup U-Boot SPL has completed, the second Device Management (DM) |
| 102 | firmware can be loaded on the now free core in the wakeup domain. |
| 103 | |
| 104 | For more information on the bootup process of your SoC, consult the |
| 105 | device specific boot flow documentation. |
| 106 | |
| 107 | Software Sources |
| 108 | ---------------- |
| 109 | |
| 110 | All scripts and code needed to build the `tiboot3.bin`, `tispl.bin` and |
| 111 | `u-boot.img` for all K3 SoCs can be located at the following places |
| 112 | online |
| 113 | |
| 114 | * **Das U-Boot** |
| 115 | |
| 116 | | **source:** https://source.denx.de/u-boot/u-boot.git |
| 117 | | **branch:** master |
| 118 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 119 | * **Trusted Firmware-A (TF-A)** |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 120 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 121 | | **source:** https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/ |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 122 | | **branch:** master |
| 123 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 124 | * **Open Portable Trusted Execution Environment (OP-TEE)** |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 125 | |
| 126 | | **source:** https://github.com/OP-TEE/optee_os.git |
| 127 | | **branch:** master |
| 128 | |
| 129 | * **TI Firmware (TIFS, DM, DSMC)** |
| 130 | |
| 131 | | **source:** https://git.ti.com/git/processor-firmware/ti-linux-firmware.git |
| 132 | | **branch:** ti-linux-firmware |
| 133 | |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 134 | Build Procedure |
| 135 | --------------- |
| 136 | |
| 137 | Depending on the specifics of your device, you will need three or more |
| 138 | binaries to boot your SoC. |
| 139 | |
| 140 | * `tiboot3.bin` (bootloader for the wakeup domain) |
| 141 | * `tispl.bin` (bootloader for the main domain) |
| 142 | * `u-boot.img` |
| 143 | |
| 144 | During the bootup process, both the 32bit wakeup domain and the 64bit |
| 145 | main domains will be involved. This means everything inside the |
| 146 | `tiboot3.bin` running in the wakeup domain will need to be compiled for |
| 147 | 32bit cores and most binaries in the `tispl.bin` will need to be |
| 148 | compiled for 64bit main domain CPU cores. |
| 149 | |
| 150 | All of that to say you will need both a 32bit and 64bit cross compiler |
| 151 | (assuming you're using an x86 desktop) |
| 152 | |
| 153 | .. code-block:: bash |
| 154 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 155 | $ export CC32=arm-linux-gnueabihf- |
| 156 | $ export CC64=aarch64-linux-gnu- |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 157 | |
| 158 | Building tiboot3.bin |
| 159 | ^^^^^^^^^^^^^^^^^^^^^ |
| 160 | |
| 161 | 1. To generate the U-Boot SPL for the wakeup domain, use the following |
| 162 | commands, substituting :code:`{SOC}` for the name of your device (eg: |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 163 | am62x) to package the various firmware and the wakeup UBoot SPL into |
| 164 | the final `tiboot3.bin` binary. (or the `sysfw.itb` if your device |
| 165 | uses the split binary flow) |
| 166 | |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 167 | |
| 168 | .. code-block:: bash |
| 169 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 170 | $ # inside u-boot source |
| 171 | $ make ARCH=arm {SOC}_evm_r5_defconfig |
| 172 | $ make ARCH=arm CROSS_COMPILE=$CC32 \ |
| 173 | BINMAN_INDIRS=<path/to/ti-linux-firmware> |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 174 | |
| 175 | At this point you should have all the needed binaries to boot the wakeup |
| 176 | domain of your K3 SoC. |
| 177 | |
| 178 | **Combined Binary Boot Flow** (eg: am62x, am64x, ... ) |
| 179 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 180 | `tiboot3-{SOC}-{gp/hs-fs/hs}.bin` |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 181 | |
| 182 | **Split Binary Boot Flow** (eg: j721e, am65x) |
| 183 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 184 | | `tiboot3-{SOC}-{gp/hs-fs/hs}.bin` |
| 185 | | `sysfw-{SOC}-{gp/hs-fs/hs}-evm.itb` |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 186 | |
| 187 | .. note :: |
| 188 | |
| 189 | It's important to rename the generated `tiboot3.bin` and `sysfw.itb` |
| 190 | to match exactly `tiboot3.bin` and `sysfw.itb` as ROM and the wakeup |
| 191 | UBoot SPL will only look for and load the files with these names. |
| 192 | |
| 193 | Building tispl.bin |
| 194 | ^^^^^^^^^^^^^^^^^^^ |
| 195 | |
| 196 | The `tispl.bin` is a standard fitImage combining the firmware need for |
| 197 | the main domain to function properly as well as Device Management (DM) |
| 198 | firmware if your device using a split firmware. |
| 199 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 200 | 2. We will first need TF-A, as it's the first thing to run on the 'big' |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 201 | application cores on the main domain. |
| 202 | |
| 203 | .. code-block:: bash |
| 204 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 205 | $ # inside trusted-firmware-a source |
| 206 | $ make CROSS_COMPILE=$CC64 ARCH=aarch64 PLAT=k3 \ |
| 207 | TARGET_BOARD={lite|generic|j784s4} \ |
| 208 | SPD=opteed |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 209 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 210 | Typically all `j7*` devices will use `TARGET_BOARD=generic` or `TARGET_BOARD |
| 211 | =j784s4` (if it is a J784S4 device), while all Sitara (`am6*`) devices |
| 212 | use the `lite` option. |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 213 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 214 | 3. The Open Portable Trusted Execution Environment (OP-TEE) is designed |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 215 | to run as a companion to a non-secure Linux kernel for Cortex-A cores |
| 216 | using the TrustZone technology built into the core. |
| 217 | |
| 218 | .. code-block:: bash |
| 219 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 220 | $ # inside optee_os source |
| 221 | $ make CROSS_COMPILE=$CC32 CROSS_COMPILE64=$CC64 \ |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 222 | PLATFORM=k3 CFG_ARM64_core=y |
| 223 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 224 | 4. Finally, after TF-A has initialized the main domain and OP-TEE has |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 225 | finished, we can jump back into U-Boot again, this time running on a |
| 226 | 64bit core in the main domain. |
| 227 | |
| 228 | .. code-block:: bash |
| 229 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 230 | $ # inside u-boot source |
| 231 | $ make ARCH=arm {SOC}_evm_a{53,72}_defconfig |
| 232 | $ make ARCH=arm CROSS_COMPILE=$CC64 \ |
| 233 | BINMAN_INDIRS=<path/to/ti-linux-firmware> \ |
| 234 | BL31=<path/to/trusted-firmware-a/dir>/build/k3/generic/release/bl31.bin \ |
| 235 | TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin |
Bryan Brattlof | 16a30b3 | 2022-12-19 14:29:50 -0600 | [diff] [blame] | 236 | |
| 237 | At this point you should have every binary needed initialize both the |
| 238 | wakeup and main domain and to boot to the U-Boot prompt |
| 239 | |
| 240 | **Main Domain Bootloader** |
| 241 | |
Neha Malcom Francis | 1ee652a | 2023-07-22 00:14:43 +0530 | [diff] [blame^] | 242 | | `tispl.bin` for HS devices or `tispl.bin_unsigned` for GP devices |
| 243 | | `u-boot.img` for HS devices or `u-boot.img_unsigned` for GP devices |