blob: 8fc81f902db92e8e493a182e11a1ab997f9173fa [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +08002/*
3 * (C) Copyright 2009 Faraday Technology
4 * Po-Yu Chuang <ratbert@faraday-tech.com>
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +08005 */
6
7/*
8 * Power Management Unit
9 */
10#ifndef __FTPMU010_H
11#define __FTPMU010_H
12
Macpaul Lind2287102011-03-20 23:44:07 +000013#ifndef __ASSEMBLY__
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080014struct ftpmu010 {
15 unsigned int IDNMBR0; /* 0x00 */
16 unsigned int reserved0; /* 0x04 */
17 unsigned int OSCC; /* 0x08 */
18 unsigned int PMODE; /* 0x0C */
19 unsigned int PMCR; /* 0x10 */
20 unsigned int PED; /* 0x14 */
21 unsigned int PEDSR; /* 0x18 */
22 unsigned int reserved1; /* 0x1C */
23 unsigned int PMSR; /* 0x20 */
24 unsigned int PGSR; /* 0x24 */
25 unsigned int MFPSR; /* 0x28 */
26 unsigned int MISC; /* 0x2C */
27 unsigned int PDLLCR0; /* 0x30 */
28 unsigned int PDLLCR1; /* 0x34 */
29 unsigned int AHBMCLKOFF; /* 0x38 */
30 unsigned int APBMCLKOFF; /* 0x3C */
31 unsigned int DCSRCR0; /* 0x40 */
32 unsigned int DCSRCR1; /* 0x44 */
33 unsigned int DCSRCR2; /* 0x48 */
34 unsigned int SDRAMHTC; /* 0x4C */
35 unsigned int PSPR0; /* 0x50 */
36 unsigned int PSPR1; /* 0x54 */
37 unsigned int PSPR2; /* 0x58 */
38 unsigned int PSPR3; /* 0x5C */
39 unsigned int PSPR4; /* 0x60 */
40 unsigned int PSPR5; /* 0x64 */
41 unsigned int PSPR6; /* 0x68 */
42 unsigned int PSPR7; /* 0x6C */
43 unsigned int PSPR8; /* 0x70 */
44 unsigned int PSPR9; /* 0x74 */
45 unsigned int PSPR10; /* 0x78 */
46 unsigned int PSPR11; /* 0x7C */
47 unsigned int PSPR12; /* 0x80 */
48 unsigned int PSPR13; /* 0x84 */
49 unsigned int PSPR14; /* 0x88 */
50 unsigned int PSPR15; /* 0x8C */
51 unsigned int AHBDMA_RACCS; /* 0x90 */
52 unsigned int reserved2; /* 0x94 */
53 unsigned int reserved3; /* 0x98 */
54 unsigned int JSS; /* 0x9C */
55 unsigned int CFC_RACC; /* 0xA0 */
56 unsigned int SSP1_RACC; /* 0xA4 */
57 unsigned int UART1TX_RACC; /* 0xA8 */
58 unsigned int UART1RX_RACC; /* 0xAC */
59 unsigned int UART2TX_RACC; /* 0xB0 */
60 unsigned int UART2RX_RACC; /* 0xB4 */
61 unsigned int SDC_RACC; /* 0xB8 */
62 unsigned int I2SAC97_RACC; /* 0xBC */
63 unsigned int IRDATX_RACC; /* 0xC0 */
64 unsigned int reserved4; /* 0xC4 */
65 unsigned int USBD_RACC; /* 0xC8 */
66 unsigned int IRDARX_RACC; /* 0xCC */
67 unsigned int IRDA_RACC; /* 0xD0 */
68 unsigned int ED0_RACC; /* 0xD4 */
69 unsigned int ED1_RACC; /* 0xD8 */
70};
Macpaul Lind2287102011-03-20 23:44:07 +000071#endif /* __ASSEMBLY__ */
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +080072
73/*
74 * ID Number 0 Register
75 */
76#define FTPMU010_ID_A320A 0x03200000
77#define FTPMU010_ID_A320C 0x03200010
78#define FTPMU010_ID_A320D 0x03200030
79
80/*
81 * OSC Control Register
82 */
83#define FTPMU010_OSCC_OSCH_TRI (1 << 11)
84#define FTPMU010_OSCC_OSCH_STABLE (1 << 9)
85#define FTPMU010_OSCC_OSCH_OFF (1 << 8)
86
87#define FTPMU010_OSCC_OSCL_TRI (1 << 3)
88#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2)
89#define FTPMU010_OSCC_OSCL_STABLE (1 << 1)
90#define FTPMU010_OSCC_OSCL_OFF (1 << 0)
91
92/*
93 * Power Mode Register
94 */
95#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4)
96#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4)
97#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4)
98#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4)
99#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4)
100#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4)
101#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7)
102#define FTPMU010_PMODE_FCS (1 << 2)
103#define FTPMU010_PMODE_TURBO (1 << 1)
104#define FTPMU010_PMODE_SLEEP (1 << 0)
105
106/*
107 * Power Manager Status Register
108 */
109#define FTPMU010_PMSR_SMR (1 << 10)
110
111#define FTPMU010_PMSR_RDH (1 << 2)
112#define FTPMU010_PMSR_PH (1 << 1)
113#define FTPMU010_PMSR_CKEHLOW (1 << 0)
114
115/*
116 * Multi-Function Port Setting Register
117 */
Macpaul Lincaddb8e2011-03-20 23:44:06 +0000118#define FTPMU010_MFPSR_DEBUGSEL (1 << 17)
119#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16)
120#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15)
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800121#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14)
122#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13)
Macpaul Lincaddb8e2011-03-20 23:44:06 +0000123#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11)
124#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10)
125#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9)
126#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8)
127#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6)
128#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5)
129#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4)
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800130#define FTPMU010_MFPSR_AC97PINSEL (1 << 3)
Macpaul Lincaddb8e2011-03-20 23:44:06 +0000131#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1)
132#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0)
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800133
134/*
135 * PLL/DLL Control Register 0
Macpaul Lincaddb8e2011-03-20 23:44:06 +0000136 * Note:
137 * 1. FTPMU010_PDLLCR0_HCLKOUTDIS:
138 * Datasheet indicated it starts at bit #21 which was wrong.
139 * 2. FTPMU010_PDLLCR0_DLLFRAG:
140 * Datasheet indicated it has 2 bit which was wrong.
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800141 */
Macpaul Lincaddb8e2011-03-20 23:44:06 +0000142#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20)
143#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19)
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800144#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18)
145#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17)
146#define FTPMU010_PDLLCR0_DLLDIS (1 << 16)
Macpaul Lincaddb8e2011-03-20 23:44:06 +0000147#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12)
148#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3)
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800149#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2)
150#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1)
151#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0)
152
Macpaul Lincaddb8e2011-03-20 23:44:06 +0000153/*
154 * SDRAM Signal Hold Time Control Register
155 */
156#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28)
157#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24)
158#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20)
159#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18)
160#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17)
161#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16)
162#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15)
163#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14)
164#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13)
165#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12)
166
Macpaul Lind2287102011-03-20 23:44:07 +0000167#ifndef __ASSEMBLY__
Po-Yu Chuangd6150db2011-02-17 19:34:07 +0000168void ftpmu010_32768osc_enable(void);
169void ftpmu010_dlldis_disable(void);
Macpaul Linac560322011-05-02 01:28:47 +0000170void ftpmu010_mfpsr_diselect_dev(unsigned int dev);
171void ftpmu010_mfpsr_select_dev(unsigned int dev);
Po-Yu Chuangd6150db2011-02-17 19:34:07 +0000172void ftpmu010_sdram_clk_disable(unsigned int cr0);
Macpaul Linac560322011-05-02 01:28:47 +0000173void ftpmu010_sdramhtc_set(unsigned int val);
Macpaul Lind2287102011-03-20 23:44:07 +0000174#endif
175
176#ifdef __ASSEMBLY__
177#define FTPMU010_IDNMBR0 0x00
178#define FTPMU010_reserved0 0x04
179#define FTPMU010_OSCC 0x08
180#define FTPMU010_PMODE 0x0C
181#define FTPMU010_PMCR 0x10
182#define FTPMU010_PED 0x14
183#define FTPMU010_PEDSR 0x18
184#define FTPMU010_reserved1 0x1C
185#define FTPMU010_PMSR 0x20
186#define FTPMU010_PGSR 0x24
187#define FTPMU010_MFPSR 0x28
188#define FTPMU010_MISC 0x2C
189#define FTPMU010_PDLLCR0 0x30
190#define FTPMU010_PDLLCR1 0x34
191#define FTPMU010_AHBMCLKOFF 0x38
192#define FTPMU010_APBMCLKOFF 0x3C
193#define FTPMU010_DCSRCR0 0x40
194#define FTPMU010_DCSRCR1 0x44
195#define FTPMU010_DCSRCR2 0x48
196#define FTPMU010_SDRAMHTC 0x4C
197#define FTPMU010_PSPR0 0x50
198#define FTPMU010_PSPR1 0x54
199#define FTPMU010_PSPR2 0x58
200#define FTPMU010_PSPR3 0x5C
201#define FTPMU010_PSPR4 0x60
202#define FTPMU010_PSPR5 0x64
203#define FTPMU010_PSPR6 0x68
204#define FTPMU010_PSPR7 0x6C
205#define FTPMU010_PSPR8 0x70
206#define FTPMU010_PSPR9 0x74
207#define FTPMU010_PSPR10 0x78
208#define FTPMU010_PSPR11 0x7C
209#define FTPMU010_PSPR12 0x80
210#define FTPMU010_PSPR13 0x84
211#define FTPMU010_PSPR14 0x88
212#define FTPMU010_PSPR15 0x8C
213#define FTPMU010_AHBDMA_RACCS 0x90
214#define FTPMU010_reserved2 0x94
215#define FTPMU010_reserved3 0x98
216#define FTPMU010_JSS 0x9C
217#define FTPMU010_CFC_RACC 0xA0
218#define FTPMU010_SSP1_RACC 0xA4
219#define FTPMU010_UART1TX_RACC 0xA8
220#define FTPMU010_UART1RX_RACC 0xAC
221#define FTPMU010_UART2TX_RACC 0xB0
222#define FTPMU010_UART2RX_RACC 0xB4
223#define FTPMU010_SDC_RACC 0xB8
224#define FTPMU010_I2SAC97_RACC 0xBC
225#define FTPMU010_IRDATX_RACC 0xC0
226#define FTPMU010_reserved4 0xC4
227#define FTPMU010_USBD_RACC 0xC8
228#define FTPMU010_IRDARX_RACC 0xCC
229#define FTPMU010_IRDA_RACC 0xD0
230#define FTPMU010_ED0_RACC 0xD4
231#define FTPMU010_ED1_RACC 0xD8
232#endif /* __ASSEMBLY__ */
Po-Yu Chuangd6150db2011-02-17 19:34:07 +0000233
Po-Yu Chuang43a5f0d2009-11-11 17:27:30 +0800234#endif /* __FTPMU010_H */