Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 2 | /* |
Wolfgang Denk | 5b5eb9c | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 3 | * (C) Copyright 2001-2008 |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 4 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 5 | * Keith Outwater, keith_outwater@mvis.com` |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) |
| 10 | * DS1337 Real Time Clock (RTC). |
| 11 | */ |
| 12 | |
| 13 | #include <common.h> |
| 14 | #include <command.h> |
| 15 | #include <rtc.h> |
| 16 | #include <i2c.h> |
| 17 | |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 18 | /* |
| 19 | * RTC register addresses |
| 20 | */ |
Kenth Eriksson | 8fde2f3 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 21 | #if defined CONFIG_RTC_DS1337 |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 22 | #define RTC_SEC_REG_ADDR 0x0 |
| 23 | #define RTC_MIN_REG_ADDR 0x1 |
| 24 | #define RTC_HR_REG_ADDR 0x2 |
| 25 | #define RTC_DAY_REG_ADDR 0x3 |
| 26 | #define RTC_DATE_REG_ADDR 0x4 |
| 27 | #define RTC_MON_REG_ADDR 0x5 |
| 28 | #define RTC_YR_REG_ADDR 0x6 |
| 29 | #define RTC_CTL_REG_ADDR 0x0e |
| 30 | #define RTC_STAT_REG_ADDR 0x0f |
Werner Pfister | b0078c8 | 2009-09-21 14:49:55 +0200 | [diff] [blame] | 31 | #define RTC_TC_REG_ADDR 0x10 |
Kenth Eriksson | 8fde2f3 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 32 | #elif defined CONFIG_RTC_DS1388 |
| 33 | #define RTC_SEC_REG_ADDR 0x1 |
| 34 | #define RTC_MIN_REG_ADDR 0x2 |
| 35 | #define RTC_HR_REG_ADDR 0x3 |
| 36 | #define RTC_DAY_REG_ADDR 0x4 |
| 37 | #define RTC_DATE_REG_ADDR 0x5 |
| 38 | #define RTC_MON_REG_ADDR 0x6 |
| 39 | #define RTC_YR_REG_ADDR 0x7 |
| 40 | #define RTC_CTL_REG_ADDR 0x0c |
| 41 | #define RTC_STAT_REG_ADDR 0x0b |
| 42 | #define RTC_TC_REG_ADDR 0x0a |
| 43 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 44 | |
| 45 | /* |
| 46 | * RTC control register bits |
| 47 | */ |
Wolfgang Denk | 5b5eb9c | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 48 | #define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */ |
| 49 | #define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */ |
| 50 | #define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */ |
| 51 | #define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */ |
| 52 | #define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */ |
| 53 | #define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 54 | |
| 55 | /* |
| 56 | * RTC status register bits |
| 57 | */ |
Wolfgang Denk | 5b5eb9c | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 58 | #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */ |
| 59 | #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */ |
| 60 | #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */ |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 61 | |
| 62 | |
| 63 | static uchar rtc_read (uchar reg); |
| 64 | static void rtc_write (uchar reg, uchar val); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 65 | |
| 66 | /* |
| 67 | * Get the current time from the RTC |
| 68 | */ |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 69 | int rtc_get (struct rtc_time *tmp) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 70 | { |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 71 | int rel = 0; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 72 | uchar sec, min, hour, mday, wday, mon_cent, year, control, status; |
| 73 | |
| 74 | control = rtc_read (RTC_CTL_REG_ADDR); |
| 75 | status = rtc_read (RTC_STAT_REG_ADDR); |
| 76 | sec = rtc_read (RTC_SEC_REG_ADDR); |
| 77 | min = rtc_read (RTC_MIN_REG_ADDR); |
| 78 | hour = rtc_read (RTC_HR_REG_ADDR); |
| 79 | wday = rtc_read (RTC_DAY_REG_ADDR); |
| 80 | mday = rtc_read (RTC_DATE_REG_ADDR); |
| 81 | mon_cent = rtc_read (RTC_MON_REG_ADDR); |
| 82 | year = rtc_read (RTC_YR_REG_ADDR); |
| 83 | |
Kenth Eriksson | 8fde2f3 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 84 | /* No century bit, assume year 2000 */ |
| 85 | #ifdef CONFIG_RTC_DS1388 |
| 86 | mon_cent |= 0x80; |
| 87 | #endif |
| 88 | |
Wolfgang Denk | 88b2533 | 2011-10-29 09:39:11 +0000 | [diff] [blame] | 89 | debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 90 | "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n", |
| 91 | year, mon_cent, mday, wday, hour, min, sec, control, status); |
| 92 | |
| 93 | if (status & RTC_STAT_BIT_OSF) { |
| 94 | printf ("### Warning: RTC oscillator has stopped\n"); |
| 95 | /* clear the OSF flag */ |
| 96 | rtc_write (RTC_STAT_REG_ADDR, |
| 97 | rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF); |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 98 | rel = -1; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 99 | } |
| 100 | |
| 101 | tmp->tm_sec = bcd2bin (sec & 0x7F); |
| 102 | tmp->tm_min = bcd2bin (min & 0x7F); |
| 103 | tmp->tm_hour = bcd2bin (hour & 0x3F); |
| 104 | tmp->tm_mday = bcd2bin (mday & 0x3F); |
| 105 | tmp->tm_mon = bcd2bin (mon_cent & 0x1F); |
| 106 | tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900); |
| 107 | tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); |
| 108 | tmp->tm_yday = 0; |
| 109 | tmp->tm_isdst= 0; |
| 110 | |
Wolfgang Denk | 88b2533 | 2011-10-29 09:39:11 +0000 | [diff] [blame] | 111 | debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 112 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 113 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
Yuri Tikhonov | b73a19e | 2008-03-20 17:56:04 +0300 | [diff] [blame] | 114 | |
| 115 | return rel; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | |
| 119 | /* |
| 120 | * Set the RTC |
| 121 | */ |
Jean-Christophe PLAGNIOL-VILLARD | d1e2319 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 122 | int rtc_set (struct rtc_time *tmp) |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 123 | { |
| 124 | uchar century; |
| 125 | |
Wolfgang Denk | 88b2533 | 2011-10-29 09:39:11 +0000 | [diff] [blame] | 126 | debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 127 | tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, |
| 128 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 129 | |
| 130 | rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); |
| 131 | |
| 132 | century = (tmp->tm_year >= 2000) ? 0x80 : 0; |
| 133 | rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century); |
| 134 | |
| 135 | rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); |
| 136 | rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); |
| 137 | rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); |
| 138 | rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); |
| 139 | rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); |
Jean-Christophe PLAGNIOL-VILLARD | d1e2319 | 2008-09-01 23:06:23 +0200 | [diff] [blame] | 140 | |
| 141 | return 0; |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 142 | } |
| 143 | |
| 144 | |
| 145 | /* |
| 146 | * Reset the RTC. We also enable the oscillator output on the |
| 147 | * SQW/INTB* pin and program it for 32,768 Hz output. Note that |
| 148 | * according to the datasheet, turning on the square wave output |
| 149 | * increases the current drain on the backup battery from about |
Chris Packham | 2bd3cab | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 150 | * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn |
Joakim Tjernlund | da8808d | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 151 | * off the OSC output. |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 152 | */ |
Kenth Eriksson | 8fde2f3 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 153 | |
Chris Packham | 2bd3cab | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 154 | #ifdef CONFIG_RTC_DS1337_NOOSC |
Joakim Tjernlund | da8808d | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 155 | #define RTC_DS1337_RESET_VAL \ |
Wolfgang Denk | 5b5eb9c | 2008-03-26 15:38:47 +0100 | [diff] [blame] | 156 | (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
Joakim Tjernlund | da8808d | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 157 | #else |
| 158 | #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2) |
| 159 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 160 | void rtc_reset (void) |
| 161 | { |
Chris Packham | 2bd3cab | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 162 | #ifdef CONFIG_RTC_DS1337 |
Joakim Tjernlund | da8808d | 2008-03-26 13:02:13 +0100 | [diff] [blame] | 163 | rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL); |
Chris Packham | 2bd3cab | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 164 | #elif defined CONFIG_RTC_DS1388 |
Kenth Eriksson | 8fde2f3 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 165 | rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */ |
| 166 | #endif |
Chris Packham | 2bd3cab | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 167 | #ifdef CONFIG_RTC_DS1339_TCR_VAL |
| 168 | rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL); |
Werner Pfister | b0078c8 | 2009-09-21 14:49:55 +0200 | [diff] [blame] | 169 | #endif |
Chris Packham | 2bd3cab | 2017-05-30 12:03:33 +1200 | [diff] [blame] | 170 | #ifdef CONFIG_RTC_DS1388_TCR_VAL |
| 171 | rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL); |
Kenth Eriksson | 8fde2f3 | 2012-07-12 19:59:44 +0000 | [diff] [blame] | 172 | #endif |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | |
| 176 | /* |
| 177 | * Helper functions |
| 178 | */ |
| 179 | |
| 180 | static |
| 181 | uchar rtc_read (uchar reg) |
| 182 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 183 | return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | |
| 187 | static void rtc_write (uchar reg, uchar val) |
| 188 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); |
wdenk | 5d3207d | 2002-08-21 22:08:56 +0000 | [diff] [blame] | 190 | } |