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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1f3555d906442b3899660c9120a89cee12ab1d06 / . / arch / arm / dts / imx6qdl-gw54xx.dtsi
blob: a30ba4848e04548b726d93716df80fa1467f5ee7 [file] [log] [blame]
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/sound/fsl-imx-audmux.h>
10
11/ {
12 /* these are used by bootloader for disabling nodes */
13 aliases {
14 led0 = &led0;
15 led1 = &led1;
16 led2 = &led2;
Tim Harvey19a387f2021-03-01 14:33:35 -0800[diff] [blame]17 mmc0 = &usdhc3;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]18 nand = &gpmi;
19 ssi0 = &ssi1;
20 usb0 = &usbh1;
21 usb1 = &usbotg;
22 };
23
24 chosen {
25 bootargs = "console=ttymxc1,115200";
26 };
27
28 backlight {
29 compatible = "pwm-backlight";
30 pwms = <&pwm4 0 5000000>;
31 brightness-levels = <0 4 8 16 32 64 128 255>;
32 default-brightness-level = <7>;
33 };
34
35 gpio-keys {
36 compatible = "gpio-keys";
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 user-pb {
41 label = "user_pb";
42 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
43 linux,code = <BTN_0>;
44 };
45
46 user-pb1x {
47 label = "user_pb1x";
48 linux,code = <BTN_1>;
49 interrupt-parent = <&gsc>;
50 interrupts = <0>;
51 };
52
53 key-erased {
54 label = "key-erased";
55 linux,code = <BTN_2>;
56 interrupt-parent = <&gsc>;
57 interrupts = <1>;
58 };
59
60 eeprom-wp {
61 label = "eeprom_wp";
62 linux,code = <BTN_3>;
63 interrupt-parent = <&gsc>;
64 interrupts = <2>;
65 };
66
67 tamper {
68 label = "tamper";
69 linux,code = <BTN_4>;
70 interrupt-parent = <&gsc>;
71 interrupts = <5>;
72 };
73
74 switch-hold {
75 label = "switch_hold";
76 linux,code = <BTN_5>;
77 interrupt-parent = <&gsc>;
78 interrupts = <7>;
79 };
80 };
81
82 leds {
83 compatible = "gpio-leds";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_gpio_leds>;
86
87 led0: user1 {
88 label = "user1";
89 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
90 default-state = "on";
91 linux,default-trigger = "heartbeat";
92 };
93
94 led1: user2 {
95 label = "user2";
96 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
97 default-state = "off";
98 };
99
100 led2: user3 {
101 label = "user3";
102 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
103 default-state = "off";
104 };
105 };
106
107 memory@10000000 {
108 device_type = "memory";
109 reg = <0x10000000 0x40000000>;
110 };
111
112 pps {
113 compatible = "pps-gpio";
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_pps>;
116 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
117 status = "okay";
118 };
119
120 regulators {
121 compatible = "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <0>;
124
125 reg_1p0v: regulator@0 {
126 compatible = "regulator-fixed";
127 reg = <0>;
128 regulator-name = "1P0V";
129 regulator-min-microvolt = <1000000>;
130 regulator-max-microvolt = <1000000>;
131 regulator-always-on;
132 };
133
134 reg_3p3v: regulator@1 {
135 compatible = "regulator-fixed";
136 reg = <1>;
137 regulator-name = "3P3V";
138 regulator-min-microvolt = <3300000>;
139 regulator-max-microvolt = <3300000>;
140 regulator-always-on;
141 };
142
143 reg_usb_h1_vbus: regulator@2 {
144 compatible = "regulator-fixed";
145 reg = <2>;
146 regulator-name = "usb_h1_vbus";
147 regulator-min-microvolt = <5000000>;
148 regulator-max-microvolt = <5000000>;
149 regulator-always-on;
150 };
151
152 reg_usb_otg_vbus: regulator@3 {
153 compatible = "regulator-fixed";
154 reg = <3>;
155 regulator-name = "usb_otg_vbus";
156 regulator-min-microvolt = <5000000>;
157 regulator-max-microvolt = <5000000>;
158 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
159 enable-active-high;
160 };
161 };
162
163 sound-analog {
164 compatible = "fsl,imx6q-ventana-sgtl5000",
165 "fsl,imx-audio-sgtl5000";
166 model = "sgtl5000-audio";
167 ssi-controller = <&ssi1>;
168 audio-codec = <&sgtl5000>;
169 audio-routing =
170 "MIC_IN", "Mic Jack",
171 "Mic Jack", "Mic Bias",
172 "Headphone Jack", "HP_OUT";
173 mux-int-port = <1>;
174 mux-ext-port = <4>;
175 };
176};
177
178&audmux {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
181 status = "okay";
182
183 ssi2 {
184 fsl,audmux-port = <1>;
185 fsl,port-config = <
186 (IMX_AUDMUX_V2_PTCR_TFSDIR |
187 IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
188 IMX_AUDMUX_V2_PTCR_TCLKDIR |
189 IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
190 IMX_AUDMUX_V2_PTCR_SYN)
191 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
192 >;
193 };
194
195 aud5 {
196 fsl,audmux-port = <4>;
197 fsl,port-config = <
198 IMX_AUDMUX_V2_PTCR_SYN
199 IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
200 };
201};
202
203&can1 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_flexcan1>;
206 status = "okay";
207};
208
209&clks {
210 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
211 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
212 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
213 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
214};
215
216&ecspi2 {
217 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_ecspi2>;
220 status = "okay";
221};
222
223&fec {
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_enet>;
226 phy-mode = "rgmii-id";
227 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
228 status = "okay";
229};
230
231&gpmi {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_gpmi_nand>;
234 status = "okay";
235};
236
237&hdmi {
238 ddc-i2c-bus = <&i2c3>;
239 status = "okay";
240};
241
242&i2c1 {
243 clock-frequency = <100000>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c1>;
246 status = "okay";
247
248 gsc: gsc@20 {
249 compatible = "gw,gsc";
250 reg = <0x20>;
251 interrupt-parent = <&gpio1>;
252 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
253 interrupt-controller;
254 #interrupt-cells = <1>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257
258 adc {
259 compatible = "gw,gsc-adc";
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 channel@0 {
264 gw,mode = <0>;
265 reg = <0x00>;
266 label = "temp";
267 };
268
269 channel@2 {
270 gw,mode = <1>;
271 reg = <0x02>;
272 label = "vdd_vin";
273 };
274
275 channel@5 {
276 gw,mode = <1>;
277 reg = <0x05>;
278 label = "vdd_3p3";
279 };
280
281 channel@8 {
282 gw,mode = <1>;
283 reg = <0x08>;
284 label = "vdd_bat";
285 };
286
287 channel@b {
288 gw,mode = <1>;
289 reg = <0x0b>;
290 label = "vdd_5p0";
291 };
292
293 channel@e {
294 gw,mode = <1>;
295 reg = <0xe>;
296 label = "vdd_arm";
297 };
298
299 channel@11 {
300 gw,mode = <1>;
301 reg = <0x11>;
302 label = "vdd_soc";
303 };
304
305 channel@14 {
306 gw,mode = <1>;
307 reg = <0x14>;
308 label = "vdd_3p0";
309 };
310
311 channel@17 {
312 gw,mode = <1>;
313 reg = <0x17>;
314 label = "vdd_1p5";
315 };
316
317 channel@1d {
318 gw,mode = <1>;
319 reg = <0x1d>;
320 label = "vdd_1p8";
321 };
322
323 channel@20 {
324 gw,mode = <1>;
325 reg = <0x20>;
326 label = "vdd_1p0";
327 };
328
329 channel@23 {
330 gw,mode = <1>;
331 reg = <0x23>;
332 label = "vdd_2p5";
333 };
334
335 channel@26 {
336 gw,mode = <1>;
337 reg = <0x26>;
338 label = "vdd_gps";
339 };
340 };
341
342 fan-controller@2c {
343 compatible = "gw,gsc-fan";
344 #address-cells = <1>;
345 #size-cells = <0>;
346 reg = <0x2c>;
347 };
348 };
349
350 gsc_gpio: gpio@23 {
351 compatible = "nxp,pca9555";
352 reg = <0x23>;
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-parent = <&gsc>;
356 interrupts = <4>;
357 };
358
359 eeprom1: eeprom@50 {
360 compatible = "atmel,24c02";
361 reg = <0x50>;
362 pagesize = <16>;
363 };
364
365 eeprom2: eeprom@51 {
366 compatible = "atmel,24c02";
367 reg = <0x51>;
368 pagesize = <16>;
369 };
370
371 eeprom3: eeprom@52 {
372 compatible = "atmel,24c02";
373 reg = <0x52>;
374 pagesize = <16>;
375 };
376
377 eeprom4: eeprom@53 {
378 compatible = "atmel,24c02";
379 reg = <0x53>;
380 pagesize = <16>;
381 };
382
383 rtc: ds1672@68 {
384 compatible = "dallas,ds1672";
385 reg = <0x68>;
386 };
387};
388
389&i2c2 {
390 clock-frequency = <100000>;
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_i2c2>;
393 status = "okay";
394
395 pmic: pfuze100@8 {
396 compatible = "fsl,pfuze100";
397 reg = <0x08>;
398
399 regulators {
400 sw1a_reg: sw1ab {
401 regulator-min-microvolt = <300000>;
402 regulator-max-microvolt = <1875000>;
403 regulator-boot-on;
404 regulator-always-on;
405 regulator-ramp-delay = <6250>;
406 };
407
408 sw1c_reg: sw1c {
409 regulator-min-microvolt = <300000>;
410 regulator-max-microvolt = <1875000>;
411 regulator-boot-on;
412 regulator-always-on;
413 regulator-ramp-delay = <6250>;
414 };
415
416 sw2_reg: sw2 {
417 regulator-min-microvolt = <800000>;
418 regulator-max-microvolt = <3950000>;
419 regulator-boot-on;
420 regulator-always-on;
421 };
422
423 sw3a_reg: sw3a {
424 regulator-min-microvolt = <400000>;
425 regulator-max-microvolt = <1975000>;
426 regulator-boot-on;
427 regulator-always-on;
428 };
429
430 sw3b_reg: sw3b {
431 regulator-min-microvolt = <400000>;
432 regulator-max-microvolt = <1975000>;
433 regulator-boot-on;
434 regulator-always-on;
435 };
436
437 sw4_reg: sw4 {
438 regulator-min-microvolt = <800000>;
439 regulator-max-microvolt = <3300000>;
440 };
441
442 swbst_reg: swbst {
443 regulator-min-microvolt = <5000000>;
444 regulator-max-microvolt = <5150000>;
445 regulator-boot-on;
446 regulator-always-on;
447 };
448
449 snvs_reg: vsnvs {
450 regulator-min-microvolt = <1000000>;
451 regulator-max-microvolt = <3000000>;
452 regulator-boot-on;
453 regulator-always-on;
454 };
455
456 vref_reg: vrefddr {
457 regulator-boot-on;
458 regulator-always-on;
459 };
460
461 vgen1_reg: vgen1 {
462 regulator-min-microvolt = <800000>;
463 regulator-max-microvolt = <1550000>;
464 };
465
466 vgen2_reg: vgen2 {
467 regulator-min-microvolt = <800000>;
468 regulator-max-microvolt = <1550000>;
469 };
470
471 vgen3_reg: vgen3 {
472 regulator-min-microvolt = <1800000>;
473 regulator-max-microvolt = <3300000>;
474 };
475
476 vgen4_reg: vgen4 {
477 regulator-min-microvolt = <1800000>;
478 regulator-max-microvolt = <3300000>;
479 regulator-always-on;
480 };
481
482 vgen5_reg: vgen5 {
483 regulator-min-microvolt = <1800000>;
484 regulator-max-microvolt = <3300000>;
485 regulator-always-on;
486 };
487
488 vgen6_reg: vgen6 {
489 regulator-min-microvolt = <1800000>;
490 regulator-max-microvolt = <3300000>;
491 regulator-always-on;
492 };
493 };
494 };
495};
496
497&i2c3 {
498 clock-frequency = <100000>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_i2c3>;
501 status = "okay";
502
503 sgtl5000: audio-codec@a {
504 compatible = "fsl,sgtl5000";
505 reg = <0x0a>;
506 clocks = <&clks IMX6QDL_CLK_CKO>;
507 VDDA-supply = <&sw4_reg>;
508 VDDIO-supply = <&reg_3p3v>;
509 };
510
511 touchscreen: egalax_ts@4 {
512 compatible = "eeti,egalax_ts";
513 reg = <0x04>;
514 interrupt-parent = <&gpio7>;
515 interrupts = <12 2>;
516 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
517 };
518
519 accel@1e {
520 compatible = "nxp,fxos8700";
521 reg = <0x1e>;
522 };
523};
524
525&ldb {
526 status = "okay";
527
528 lvds-channel@0 {
529 fsl,data-mapping = "spwg";
530 fsl,data-width = <18>;
531 status = "okay";
532
533 display-timings {
534 native-mode = <&timing0>;
535 timing0: hsd100pxn1 {
536 clock-frequency = <65000000>;
537 hactive = <1024>;
538 vactive = <768>;
539 hback-porch = <220>;
540 hfront-porch = <40>;
541 vback-porch = <21>;
542 vfront-porch = <7>;
543 hsync-len = <60>;
544 vsync-len = <10>;
545 };
546 };
547 };
548};
549
550&pcie {
551 pinctrl-names = "default";
552 pinctrl-0 = <&pinctrl_pcie>;
553 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
554 status = "okay";
555};
556
557&pwm1 {
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
560 status = "disabled";
561};
562
563&pwm2 {
564 pinctrl-names = "default";
565 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
566 status = "disabled";
567};
568
569&pwm3 {
570 pinctrl-names = "default";
571 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
572 status = "disabled";
573};
574
575&pwm4 {
576 #pwm-cells = <2>;
577 pinctrl-names = "default", "state_dio";
578 pinctrl-0 = <&pinctrl_pwm4_backlight>;
579 pinctrl-1 = <&pinctrl_pwm4_dio>;
580 status = "okay";
581};
582
583&ssi1 {
584 status = "okay";
585};
586
587&ssi2 {
588 status = "okay";
589};
590
591&uart1 {
592 pinctrl-names = "default";
593 pinctrl-0 = <&pinctrl_uart1>;
594 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
595 status = "okay";
596};
597
598&uart2 {
599 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_uart2>;
601 status = "okay";
602};
603
604&uart5 {
605 pinctrl-names = "default";
606 pinctrl-0 = <&pinctrl_uart5>;
607 status = "okay";
608};
609
610&usbotg {
611 vbus-supply = <&reg_usb_otg_vbus>;
612 pinctrl-names = "default";
613 pinctrl-0 = <&pinctrl_usbotg>;
614 disable-over-current;
Tim Harvey13acc632021-03-01 14:33:31 -0800[diff] [blame]615 dr_mode = "otg";
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]616 status = "okay";
617};
618
619&usbh1 {
620 vbus-supply = <&reg_usb_h1_vbus>;
621 status = "okay";
622};
623
624&usdhc3 {
625 pinctrl-names = "default", "state_100mhz", "state_200mhz";
626 pinctrl-0 = <&pinctrl_usdhc3>;
627 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
628 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
629 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
630 vmmc-supply = <&reg_3p3v>;
631 no-1-8-v; /* firmware will remove if board revision supports */
632 status = "okay";
633};
634
635&wdog1 {
636 status = "disabled";
637};
638
639&wdog2 {
640 pinctrl-names = "default";
641 pinctrl-0 = <&pinctrl_wdog>;
642 fsl,ext-reset-output;
643 status = "okay";
644};
645
646&iomuxc {
647 pinctrl_audmux: audmuxgrp {
648 fsl,pins = <
649 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
650 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
651 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
652 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
653 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
654 MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
655 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
656 MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
657 >;
658 };
659
660 pinctrl_enet: enetgrp {
661 fsl,pins = <
662 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
663 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
664 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
665 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
666 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
667 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
668 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
669 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
670 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
671 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
672 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
673 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
674 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
675 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
676 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
677 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
678 >;
679 };
680
681 pinctrl_ecspi2: escpi2grp {
682 fsl,pins = <
683 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
684 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
685 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
686 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
687 >;
688 };
689
690 pinctrl_flexcan1: flexcan1grp {
691 fsl,pins = <
692 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
693 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
694 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
695 >;
696 };
697
698 pinctrl_gpio_leds: gpioledsgrp {
699 fsl,pins = <
700 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
701 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
702 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
703 >;
704 };
705
706 pinctrl_gpmi_nand: gpminandgrp {
707 fsl,pins = <
708 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
709 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
710 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
711 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
712 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
713 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
714 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
715 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
716 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
717 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
718 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
719 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
720 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
721 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
722 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
723 >;
724 };
725
726 pinctrl_i2c1: i2c1grp {
727 fsl,pins = <
728 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
729 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
730 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
731 >;
732 };
733
734 pinctrl_i2c2: i2c2grp {
735 fsl,pins = <
736 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
737 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
738 >;
739 };
740
741 pinctrl_i2c3: i2c3grp {
742 fsl,pins = <
743 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
744 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
745 >;
746 };
747
748 pinctrl_pcie: pciegrp {
749 fsl,pins = <
750 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
751 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
752 >;
753 };
754
755 pinctrl_pps: ppsgrp {
756 fsl,pins = <
757 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
758 >;
759 };
760
761 pinctrl_pwm1: pwm1grp {
762 fsl,pins = <
763 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
764 >;
765 };
766
767 pinctrl_pwm2: pwm2grp {
768 fsl,pins = <
769 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
770 >;
771 };
772
773 pinctrl_pwm3: pwm3grp {
774 fsl,pins = <
775 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
776 >;
777 };
778
779 pinctrl_pwm4_backlight: pwm4grpbacklight {
780 fsl,pins = <
781 /* LVDS_PWM J6.5 */
782 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
783 >;
784 };
785
786 pinctrl_pwm4_dio: pwm4grpdio {
787 fsl,pins = <
788 /* DIO3 J16.4 */
789 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
790 >;
791 };
792
793 pinctrl_uart1: uart1grp {
794 fsl,pins = <
795 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
796 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
797 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
798 >;
799 };
800
801 pinctrl_uart2: uart2grp {
802 fsl,pins = <
803 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
804 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
805 >;
806 };
807
808 pinctrl_uart5: uart5grp {
809 fsl,pins = <
810 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
811 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
812 >;
813 };
814
815 pinctrl_usbotg: usbotggrp {
816 fsl,pins = <
817 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
818 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
819 >;
820 };
821
822 pinctrl_usdhc3: usdhc3grp {
823 fsl,pins = <
824 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
825 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
826 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
827 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
828 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
829 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
830 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
831 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
832 >;
833 };
834
835 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
836 fsl,pins = <
837 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
838 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
839 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
840 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
841 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
842 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
843 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
844 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
845 >;
846 };
847
848 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
849 fsl,pins = <
850 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
851 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
852 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
853 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
854 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
855 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
856 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
857 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
858 >;
859 };
860
861 pinctrl_wdog: wdoggrp {
862 fsl,pins = <
863 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
864 >;
865 };
866};