blob: c251d9d59424d5e40d98abec4623dfa45ce830aa [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glasse2e947f2015-08-30 16:55:42 -06002/*
3 * Google Veyron Jerry Rev 3+ board device tree source
4 *
5 * Copyright 2014 Google, Inc
Simon Glasse2e947f2015-08-30 16:55:42 -06006 */
7
8/dts-v1/;
9#include "rk3288-veyron-chromebook.dtsi"
10#include "cros-ec-sbs.dtsi"
11
12/ {
13 model = "Google Jerry";
14 compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
15 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
16 "google,veyron-jerry-rev3", "google,veyron-jerry",
17 "google,veyron", "rockchip,rk3288";
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
Simon Glass32384742017-05-31 17:57:26 -060023 panel_regulator: panel-regulator {
Simon Glasse2e947f2015-08-30 16:55:42 -060024 compatible = "regulator-fixed";
25 enable-active-high;
26 gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default";
28 pinctrl-0 = <&lcd_enable_h>;
29 regulator-name = "panel_regulator";
30 vin-supply = <&vcc33_sys>;
31 };
32
33 vcc18_lcd: vcc18-lcd {
34 compatible = "regulator-fixed";
35 enable-active-high;
36 gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&avdd_1v8_disp_en>;
39 regulator-name = "vcc18_lcd";
40 regulator-always-on;
41 regulator-boot-on;
42 vin-supply = <&vcc18_wl>;
43 };
44
45 backlight_regulator: backlight-regulator {
46 compatible = "regulator-fixed";
47 enable-active-high;
48 gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&bl_pwr_en>;
51 regulator-name = "backlight_regulator";
52 vin-supply = <&vcc33_sys>;
53 startup-delay-us = <15000>;
54 };
Simon Glass2d0c01b2018-12-27 20:15:23 -070055
56 sound {
57 compatible = "rockchip,audio-max98090-jerry";
58
59 cpu {
60 sound-dai = <&i2s 0>;
61 };
62
63 codec {
64 sound-dai = <&max98090 0>;
65 };
66 };
Simon Glasse2e947f2015-08-30 16:55:42 -060067};
68
Simon Glassaede3ac2016-11-13 14:22:12 -070069&dmc {
70 rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
71 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
72 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
73 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
74 0x5 0x0>;
75 rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
76 0xa60 0x40 0x10 0x0>;
77 rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
78};
79
Simon Glasse2e947f2015-08-30 16:55:42 -060080&gpio_keys {
81 power {
82 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
83 };
84};
85
86&backlight {
87 power-supply = <&backlight_regulator>;
88};
89
90&panel {
91 power-supply= <&panel_regulator>;
92};
93
94&rk808 {
95 pinctrl-names = "default";
96 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
97 dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
98 <&gpio7 15 GPIO_ACTIVE_HIGH>;
99
100 regulators {
101 mic_vcc: LDO_REG2 {
102 regulator-always-on;
103 regulator-boot-on;
104 regulator-min-microvolt = <1800000>;
105 regulator-max-microvolt = <1800000>;
106 regulator-name = "mic_vcc";
107 regulator-suspend-mem-disabled;
108 };
109 };
110};
111
112&sdmmc {
113 pinctrl-names = "default";
114 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
115 &sdmmc_bus4>;
116 disable-wp;
117};
118
119&vcc_5v {
120 enable-active-high;
121 gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&drv_5v>;
124};
125
126&vcc50_hdmi {
127 enable-active-high;
128 gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&vcc50_hdmi_en>;
131};
132
Simon Glasse2e947f2015-08-30 16:55:42 -0600133&edp {
134 pinctrl-names = "default";
135 pinctrl-0 = <&edp_hpd>;
136};
137
138&pinctrl {
139 backlight {
140 bl_pwr_en: bl_pwr_en {
141 rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
142 };
143 };
144
145 buck-5v {
146 drv_5v: drv-5v {
147 rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
148 };
149 };
150
151 edp {
152 edp_hpd: edp_hpd {
153 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
154 };
155 };
156
157 emmc {
158 /* Make sure eMMC is not in reset */
159 emmc_deassert_reset: emmc-deassert-reset {
160 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
161 };
162 };
163
164 hdmi {
165 vcc50_hdmi_en: vcc50-hdmi-en {
166 rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
167 };
168 };
169
170 lcd {
171 lcd_enable_h: lcd-en {
172 rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
173 };
174
175 avdd_1v8_disp_en: avdd-1v8-disp-en {
176 rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
177 };
178 };
179
180 pmic {
181 dvs_1: dvs-1 {
182 rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
183 };
184
185 dvs_2: dvs-2 {
186 rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
187 };
188 };
189};
190
191&i2c4 {
192 status = "okay";
193
194 /*
195 * Trackpad pin control is shared between Elan and Synaptics devices
196 * so we have to pull it up to the bus level.
197 */
198 pinctrl-names = "default";
199 pinctrl-0 = <&i2c4_xfer &trackpad_int>;
200
201 trackpad@15 {
202 compatible = "elan,i2c_touchpad";
203 interrupt-parent = <&gpio7>;
204 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
205 /*
206 * Remove the inherited pinctrl settings to avoid clashing
207 * with bus-wide ones.
208 */
209 /delete-property/pinctrl-names;
210 /delete-property/pinctrl-0;
211 reg = <0x15>;
212 vcc-supply = <&vcc33_io>;
213 wakeup-source;
214 };
215
216 trackpad@2c {
217 compatible = "hid-over-i2c";
218 interrupt-parent = <&gpio7>;
219 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
220 reg = <0x2c>;
221 hid-descr-addr = <0x0020>;
222 vcc-supply = <&vcc33_io>;
223 wakeup-source;
224 };
225};