blob: 315313854254db43a266e5f048060e94f4f71196 [file] [log] [blame]
Michal Simekbe972b22019-04-11 10:35:37 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 board RevA";
17 compatible = "xlnx,zynqmp-a2197-revA", "xlnx,zynqmp-a2197", "xlnx,zynqmp";
18
19 aliases {
20 i2c0 = &i2c0;
21 serial0 = &uart0;
22 };
23
24 chosen {
25 bootargs = "earlycon";
26 stdout-path = "serial0:115200n8";
27 xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;
28 };
29
30 memory@0 {
31 device_type = "memory";
32 reg = <0x0 0x0 0x0 0x80000000>;
33 };
34};
35
36&uart0 { /* uart0 MIO38-39 */
37 status = "okay";
38 u-boot,dm-pre-reloc;
39};
40
41&i2c0 {
42 status = "okay";
43 u-boot,dm-pre-reloc;
44 clock-frequency = <400000>;
45 i2c-mux@74 { /* this cover MGT board */
46 compatible = "nxp,pca9548";
47 #address-cells = <1>;
48 #size-cells = <0>;
49 reg = <0x74>;
50 u-boot,dm-pre-reloc;
51 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
52 i2c@0 {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 reg = <0>;
56 /* Use for storing information about SC board */
57 eeprom0: eeprom@50 { /* u96 - 24LC32A - 256B */
58 compatible = "atmel,24c32";
59 u-boot,dm-pre-reloc;
60 reg = <0x50>;
61 };
62 };
63 };
64};
65
66&i2c1 {
67 status = "okay";
68 u-boot,dm-pre-reloc;
69 clock-frequency = <400000>;
70 i2c-mux@74 { /* This cover processor board */
71 compatible = "nxp,pca9548";
72 #address-cells = <1>;
73 #size-cells = <0>;
74 reg = <0x74>;
75 u-boot,dm-pre-reloc;
76 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
77 i2c@0 {
78 #address-cells = <1>;
79 #size-cells = <0>;
80 reg = <0>;
81 /* Use for storing information about SC board */
82 eeprom1: eeprom@50 { /* u96 - 24LC32A - 256B */
83 compatible = "atmel,24c32";
84 u-boot,dm-pre-reloc;
85 reg = <0x50>;
86 };
87 };
88 };
89};