blob: 69a2174871b1f32ce9a1b4a0957bd658a7722b3b [file] [log] [blame]
wdenkbb0f96b2002-02-17 23:48:45 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * 74xx_7xx.h
26 *
27 * 74xx/7xx specific definitions
28 */
29
30#ifndef __MPC74XX_H__
31#define __MPC74XX_H__
32
33/*----------------------------------------------------------------
34 * Exception offsets (PowerPC standard)
35 */
36#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
Rafal Jaworowski02032e82007-06-22 14:58:04 +020037#define _START_OFFSET EXC_OFF_SYS_RESET
wdenkbb0f96b2002-02-17 23:48:45 +000038
39/*----------------------------------------------------------------
40 * l2cr values
41 */
42#define l2cr 1017
43
44#define L2CR_L2E 0x80000000 /* bit 0 - enable */
45#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
46#define L2CR_L2SIZ_2M 0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
47#define L2CR_L2SIZ_1M 0x30000000 /* ... 1MB */
48#define L2CR_L2SIZ_HM 0x20000000 /* ... 512K */
49#define L2CR_L2SIZ_QM 0x10000000 /* ... 256k */
50#define L2CR_L2CLK_1 0x02000000 /* bits 4-6 clock ratio div 1 */
51#define L2CR_L2CLK_1_5 0x04000000 /* bits 4-6 clock ratio div 1.5 */
52#define L2CR_L2CLK_2 0x08000000 /* bits 4-6 clock ratio div 2 */
53#define L2CR_L2CLK_2_5 0x0a000000 /* bits 4-6 clock ratio div 2.5 */
54#define L2CR_L2CLK_3 0x0c000000 /* bits 4-6 clock ratio div 3 */
55#define L2CR_L2CLK_3_5 0x06000000 /* bits 4-6 clock ratio div 3.5 */
56#define L2CR_L2CLK_4 0x0e000000 /* bits 4-6 clock ratio div 4 */
57#define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
58#define L2CR_DO 0x00400000 /* bit 9 - enable caching of instr. in L2 */
59#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
60#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
61#define L2CR_L2WT 0x00080000 /* bit 12 - l2 write-through */
62#define L2CR_TS 0x00040000 /* bit 13 - test support on */
63#define L2CR_TS_OFF -L2CR_TS /* bit 13 - test support off */
64#define L2CR_L2OH_5 0x00000000 /* bits 14-15 - output hold time = short */
65#define L2CR_L2OH_1 0x00010000 /* bits 14-15 - output hold time = medium */
66#define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */
67#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
68
wdenkbb0f96b2002-02-17 23:48:45 +000069#ifndef __ASSEMBLY__
70/* cpu ids we detect */
71typedef enum __cpu_t {
72 CPU_740, CPU_750,
73 CPU_740P, CPU_750P,
74 CPU_745, CPU_755,
wdenk3a473b22004-01-03 00:43:19 +000075 CPU_750CX, CPU_750FX, CPU_750GX,
wdenkbb0f96b2002-02-17 23:48:45 +000076 CPU_7400,
77 CPU_7410,
roy zang4c527832006-11-02 18:49:51 +080078 CPU_7447A, CPU_7448,
roy zang9d27b3a2006-12-04 17:56:59 +080079 CPU_7450, CPU_7455, CPU_7457,
wdenkbb0f96b2002-02-17 23:48:45 +000080 CPU_UNKNOWN} cpu_t;
81
82extern cpu_t get_cpu_type(void);
83
84#define l1icache_enable icache_enable
85
86void l2cache_enable(void);
87void l1dcache_enable(void);
88
89static __inline__ unsigned long get_msr (void)
90{
91 unsigned long msr;
92 asm volatile("mfmsr %0" : "=r" (msr) :);
93 return msr;
94}
95
96static __inline__ void set_msr (unsigned long msr)
97{
98 asm volatile("mtmsr %0" : : "r" (msr));
99}
100
101static __inline__ unsigned long get_hid0 (void)
102{
103 unsigned long hid0;
104 asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
105 return hid0;
106}
107
108static __inline__ unsigned long get_hid1 (void)
109{
110 unsigned long hid1;
111 asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
112 return hid1;
113}
114
115static __inline__ void set_hid0 (unsigned long hid0)
116{
117 asm volatile("mtspr 1008, %0" : : "r" (hid0));
118}
119
120static __inline__ void set_hid1 (unsigned long hid1)
121{
122 asm volatile("mtspr 1009, %0" : : "r" (hid1));
123}
124
125#endif /* __ASSEMBLY__ */
126#endif /* __MPC74XX_H__ */