Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1f54ce6df8e5dcecdb7c9112f08eadd0885d3f31 / . / include / configs / CPCI750.h
blob: 45fcee00f55b339be9539a3daa4d6844af63df70 [file] [log] [blame]
stroesea20b27a2004-12-16 18:05:42 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/*************************************************************************
29 * (c) 2004 esd gmbh Hannover
30 *
31 *
32 * from db64360.h file
33 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
34 *
35 ************************************************************************/
36
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
41#include <asm/processor.h>
42
43/* This define must be before the core.h include */
44#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
45
46#ifndef __ASSEMBLY__
47#include <../board/Marvell/include/core.h>
48#endif
49/*-----------------------------------------------------*/
50
51#include "../board/esd/cpci750/local.h"
52
53/*
54 * High Level Configuration Options
55 * (easy to change)
56 */
57
58#define CONFIG_750FX /* we have a 750FX (override local.h) */
59
60#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
61
62#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
63
64#undef CONFIG_ECC /* enable ECC support */
65
66/* which initialization functions to call for this board */
67#define CONFIG_MISC_INIT_R
68#define CONFIG_BOARD_PRE_INIT
69#define CONFIG_BOARD_EARLY_INIT_F 1
70
71#define CFG_BOARD_NAME "CPCI750"
72#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
73
74/*#define CFG_HUSH_PARSER*/
75#undef CFG_HUSH_PARSER
76
77#define CFG_PROMPT_HUSH_PS2 "> "
78
79/* Define which ETH port will be used for connecting the network */
80#define CFG_ETH_PORT ETH_0
81
82/*
83 * The following defines let you select what serial you want to use
84 * for your console driver.
85 *
86 * what to do:
87 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
88 * cable onto the second DUART channel, change the CFG_DUART port from 1
89 * to 0 below.
90 *
91 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
92 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
93 */
94#define CONFIG_MPSC
95#define CONFIG_MPSC_PORT 0
96
97/* to change the default ethernet port, use this define (options: 0, 1, 2) */
98#define CONFIG_NET_MULTI
99#define MV_ETH_DEVS 1
100#define CONFIG_ETHER_PORT 0
101
102#undef CONFIG_ETHER_PORT_MII /* use RMII */
103
104#define CONFIG_BOOTDELAY 5 /* autoboot disabled */
105
106#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
107
108#define CONFIG_ZERO_BOOTDELAY_CHECK
109
110
111#undef CONFIG_BOOTARGS
112
113/* -----------------------------------------------------------------------------
114 * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
115 */
116
117#define CONFIG_IPADDR "192.168.0.185"
118
119#define CONFIG_SERIAL "AA000001"
120#define CONFIG_SERVERIP "10.0.0.79"
121#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
122
123#define CONFIG_TESTDRAMDATA y
124#define CONFIG_TESTDRAMADDRESS n
125#define CONFIG_TESETDRAMWALK n
126
127/* ----------------------------------------------------------------------------- */
128
129
130#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
131#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
132
133#undef CONFIG_WATCHDOG /* watchdog disabled */
134#undef CONFIG_ALTIVEC /* undef to disable */
135
136#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
137 CONFIG_BOOTP_BOOTFILESIZE)
138
139
140#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
141 | CFG_CMD_ASKENV \
142 | CFG_CMD_I2C \
143 | CFG_CMD_CACHE \
144 | CFG_CMD_EEPROM \
145 | CFG_CMD_PCI \
146 | CFG_CMD_ELF \
147 | CFG_CMD_DATE \
148 | CFG_CMD_NET \
149 | CFG_CMD_PING \
150 | CFG_CMD_IDE \
151 | CFG_CMD_FAT \
152 | CFG_CMD_EXT2 \
153 )
154
155#define CONFIG_DOS_PARTITION
156
157/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
158#include <cmd_confdefs.h>
159
160/*
161 * Miscellaneous configurable options
162 */
163#define CFG_I2C_EEPROM_ADDR_LEN 2
164#define CFG_I2C_MULTI_EEPROMS
165#define CFG_I2C_SPEED 80000 /* I2C speed default */
166
167#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
168#define CFG_LONGHELP /* undef to save memory */
169#define CFG_PROMPT "=> " /* Monitor Command Prompt */
170#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
171#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
172#else
173#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
174#endif
175#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
176#define CFG_MAXARGS 16 /* max number of command args */
177#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
178
179/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */
180/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
181/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
182
183/*
184#define CFG_DRAM_TEST
185 * DRAM tests
186 * CFG_DRAM_TEST - enables the following tests.
187 *
188 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
189 * Environment variable 'test_dram_data' must be
190 * set to 'y'.
191 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
192 * addressable. Environment variable
193 * 'test_dram_address' must be set to 'y'.
194 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
195 * This test takes about 6 minutes to test 64 MB.
196 * Environment variable 'test_dram_walk' must be
197 * set to 'y'.
198 */
199#define CFG_DRAM_TEST
200#if defined(CFG_DRAM_TEST)
201#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
202/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
203#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
204#define CFG_DRAM_TEST_DATA
205#define CFG_DRAM_TEST_ADDRESS
206#define CFG_DRAM_TEST_WALK
207#endif /* CFG_DRAM_TEST */
208
209#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
210#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
211
212#define CFG_LOAD_ADDR 0x00300000 /* default load address */
213
214#define CFG_HZ 1000 /* decr freq: 1ms ticks */
215#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
216#define CFG_BUS_CLK CFG_BUS_HZ
217
218#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
219
220#define CFG_TCLK 133000000
221
222/*#define CFG_750FX_HID0 0x8000c084*/
223#define CFG_750FX_HID0 0x80008484
224#define CFG_750FX_HID1 0x54800000
225#define CFG_750FX_HID2 0x00000000
226
227/*
228 * Low Level Configuration Settings
229 * (address mappings, register initial values, etc.)
230 * You should know what you are doing if you make changes here.
231 */
232
233/*-----------------------------------------------------------------------
234 * Definitions for initial stack pointer and data area
235 */
236
237 /*
238 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
239 * To an unused memory region. The stack will remain in cache until RAM
240 * is initialized
241*/
242#undef CFG_INIT_RAM_LOCK
243/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
244/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
245#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
246#define CFG_INIT_RAM_END 0x1000
247#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
248#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
249
250#define RELOCATE_INTERNAL_RAM_ADDR
251#ifdef RELOCATE_INTERNAL_RAM_ADDR
252/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
253#define CFG_INTERNAL_RAM_ADDR 0xf1080000
254#endif
255
256/*-----------------------------------------------------------------------
257 * Start addresses for the final memory configuration
258 * (Set up by the startup code)
259 * Please note that CFG_SDRAM_BASE _must_ start at 0
260 */
261#define CFG_SDRAM_BASE 0x00000000
262/* Dummies for BAT 4-7 */
263#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
264#define CFG_SDRAM2_BASE 0x20000000
265#define CFG_SDRAM3_BASE 0x30000000
266#define CFG_SDRAM4_BASE 0x40000000
267#define CFG_RESET_ADDRESS 0xfff00100
268#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
269#define CFG_MONITOR_BASE 0xfff00000
270#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
271
272/*-----------------------------------------------------------------------
273 * FLASH related
274 *----------------------------------------------------------------------*/
275
276#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
277#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
278#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
279#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */
280#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
281#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
282#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
283
284/* areas to map different things with the GT in physical space */
285#define CFG_DRAM_BANKS 4
286
287/* What to put in the bats. */
288#define CFG_MISC_REGION_BASE 0xf0000000
289
290/* Peripheral Device section */
291
292/*******************************************************/
293/* We have on the cpci750 Board : */
294/* GT-Chipset Register Area */
295/* GT-Chipset internal SRAM 256k */
296/* SRAM on external device module */
297/* Real time clock on external device module */
298/* dobble UART on external device module */
299/* Data flash on external device module */
300/* Boot flash on external device module */
301/*******************************************************/
302#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
303#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
304
305#undef MARVEL_STANDARD_CFG
306#ifndef MARVEL_STANDARD_CFG
307/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
308#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
309/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
310#define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */
311
312#define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */
313#define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */
314#define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */
315#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
316#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
317
318#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */
319#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */
320#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */
321#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */
322#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */
323
324/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
325#endif
326
327/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
328#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
329#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
330#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
331#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */
332#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
333
334 /* c 4 a 8 2 4 1 c */
335 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
336 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
337 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
338 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
339
340
341/* MPP Control MV64360 Appendix P P. 632*/
342#define CFG_MPP_CONTROL_0 0x00002222 /* */
343#define CFG_MPP_CONTROL_1 0x11110000 /* */
344#define CFG_MPP_CONTROL_2 0x11111111 /* */
345#define CFG_MPP_CONTROL_3 0x00001111 /* */
346/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */
347
348
349#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
350
351/* setup new config_value for MV64360 DDR-RAM To_do !! */
352/*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */
353/*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */
354 /* GB has high prio.
355 idma has low prio
356 MPSC has low prio
357 pci has low prio 1 and 2
358 cpu has high prio
359 Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
360 ECC disable
361 non registered DRAM */
362 /* 31:26 25:22 21:20 19 18 17 16 */
363 /* 100001 0000 010 0 0 0 0 */
364 /* refresh_count=0x400
365 phisical interleaving disable
366 virtual interleaving enable */
367 /* 15 14 13:0 */
368 /* 0 1 0x400 */
369# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
370
371
372/*-----------------------------------------------------------------------
373 * PCI stuff
374 *-----------------------------------------------------------------------
375 */
376
377#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
378#define PCI_HOST_FORCE 1 /* configure as pci host */
379#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
380
381#define CONFIG_PCI /* include pci support */
382#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
383#define CONFIG_PCI_PNP /* do pci plug-and-play */
384#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
385
386/* PCI MEMORY MAP section */
387#define CFG_PCI0_MEM_BASE 0x80000000
388#define CFG_PCI0_MEM_SIZE _128M
389#define CFG_PCI1_MEM_BASE 0x88000000
390#define CFG_PCI1_MEM_SIZE _128M
391
392#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
393#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
394
395
396
397/* PCI I/O MAP section */
398#define CFG_PCI0_IO_BASE 0xfa000000
399#define CFG_PCI0_IO_SIZE _16M
400#define CFG_PCI1_IO_BASE 0xfb000000
401#define CFG_PCI1_IO_SIZE _16M
402
403#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
404#define CFG_PCI0_IO_SPACE_PCI 0x00000000
405#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
406#define CFG_PCI1_IO_SPACE_PCI 0x00000000
407
408#if defined (CONFIG_750CX)
409#define CFG_PCI_IDSEL 0x0
410#else
411#define CFG_PCI_IDSEL 0x30
412#endif
413
414/*-----------------------------------------------------------------------
415 * IDE/ATA stuff
416 *-----------------------------------------------------------------------
417 */
418#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
419#undef CONFIG_IDE_LED /* no led for ide supported */
420#define CONFIG_IDE_RESET /* no reset for ide supported */
421#define CONFIG_IDE_PREINIT /* check for units */
422
423#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */
424#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
425
426#define CFG_ATA_BASE_ADDR 0
427#define CFG_ATA_IDE0_OFFSET 0
428#define CFG_ATA_IDE1_OFFSET 0
429
430#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
431#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
432#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
433
434
435/*----------------------------------------------------------------------
436 * Initial BAT mappings
437 */
438
439/* NOTES:
440 * 1) GUARDED and WRITE_THRU not allowed in IBATS
441 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
442 */
443
444/* SDRAM */
445#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
446#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
447#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
448#define CFG_DBAT0U CFG_IBAT0U
449
450/* init ram */
451#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
452#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
453#define CFG_DBAT1L CFG_IBAT1L
454#define CFG_DBAT1U CFG_IBAT1U
455
456/* PCI0, PCI1 in one BAT */
457#define CFG_IBAT2L BATL_NO_ACCESS
458#define CFG_IBAT2U CFG_DBAT2U
459#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
460#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
461
462/* GT regs, bootrom, all the devices, PCI I/O */
463#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
464#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
465#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
466#define CFG_DBAT3U CFG_IBAT3U
467
468/*
469 * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
470 * IBAT4 and DBAT4
471 * FIXME: ingo disable BATs for Linux Kernel
472 */
473#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */
474/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */
475
476#ifdef SETUP_HIGH_BATS_FX750
477#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
478#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
479#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
480#define CFG_DBAT4U CFG_IBAT4U
481
482/* IBAT5 and DBAT5 */
483#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
484#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
485#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
486#define CFG_DBAT5U CFG_IBAT5U
487
488/* IBAT6 and DBAT6 */
489#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
490#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
491#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
492#define CFG_DBAT6U CFG_IBAT6U
493
494/* IBAT7 and DBAT7 */
495#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
496#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
497#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
498#define CFG_DBAT7U CFG_IBAT7U
499
500#else /* set em out of range for Linux !!!!!!!!!!! */
501#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
502#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
503#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
504#define CFG_DBAT4U CFG_IBAT4U
505
506/* IBAT5 and DBAT5 */
507#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
508#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
509#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
510#define CFG_DBAT5U CFG_IBAT4U
511
512/* IBAT6 and DBAT6 */
513#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
514#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
515#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
516#define CFG_DBAT6U CFG_IBAT4U
517
518/* IBAT7 and DBAT7 */
519#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
520#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
521#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
522#define CFG_DBAT7U CFG_IBAT4U
523
524#endif
525/* FIXME: ingo end: disable BATs for Linux Kernel */
526
527/* I2C addresses for the two DIMM SPD chips */
528#define DIMM0_I2C_ADDR 0x51
529#define DIMM1_I2C_ADDR 0x52
530
531/*
532 * For booting Linux, the board info and command line data
533 * have to be in the first 8 MB of memory, since this is
534 * the maximum mapped by the Linux kernel during initialization.
535 */
536#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
537
538/*-----------------------------------------------------------------------
539 * FLASH organization
540 */
541#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */
542
543#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
544#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
545#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
546
547#if 0
548#define CFG_ENV_IS_IN_FLASH 0
549#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
550#define CFG_ENV_SECT_SIZE 0x10000
551#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
552/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
553#endif
554
555#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
556#define CFG_EEPROM_PAGE_WRITE_BITS 5
557#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
558#define CFG_I2C_EEPROM_ADDR 0x050
559#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
560#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
561
562#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
563#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
564#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
565
566/*-----------------------------------------------------------------------
567 * Cache Configuration
568 */
569#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
570#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
571#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
572#endif
573
574/*-----------------------------------------------------------------------
575 * L2CR setup -- make sure this is right for your board!
576 * look in include/mpc74xx.h for the defines used here
577 */
578
579/*#define CFG_L2*/
580#undef CFG_L2
581
582/* #ifdef CONFIG_750CX*/
583#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
584#define L2_INIT 0
585#else
586#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
587 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
588#endif
589
590#define L2_ENABLE (L2_INIT | L2CR_L2E)
591
592/*
593 * Internal Definitions
594 *
595 * Boot Flags
596 */
597#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
598#define BOOTFLAG_WARM 0x02 /* Software reboot */
599
600#define CFG_BOARD_ASM_INIT 1
601
602#endif /* __CONFIG_H */