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Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04001/*
2 * (C) Copyright 2010
3 * ISEE 2007 SL, <www.iseebcn.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#ifndef __CONFIG_H
22#define __CONFIG_H
23#include <asm/sizes.h>
24
25/*
26 * High Level Configuration Options
27 */
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040028#define CONFIG_OMAP 1 /* in a TI OMAP core */
29#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040030#define CONFIG_OMAP3_IGEP0020 1 /* working with IGEP0020 */
31
32#define CONFIG_SDRC /* The chip has SDRC controller */
33
34#include <asm/arch/cpu.h>
35#include <asm/arch/omap3.h>
36
37/*
38 * Display CPU and Board information
39 */
40#define CONFIG_DISPLAY_CPUINFO 1
41#define CONFIG_DISPLAY_BOARDINFO 1
42
43/* Clock Defines */
44#define V_OSCK 26000000 /* Clock output from T2 */
45#define V_SCLK (V_OSCK >> 1)
46
47#define CONFIG_MISC_INIT_R
48
49#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
50#define CONFIG_SETUP_MEMORY_TAGS 1
51#define CONFIG_INITRD_TAG 1
52#define CONFIG_REVISION_TAG 1
53
Grant Likely2fa8ca92011-03-28 09:59:07 +000054#define CONFIG_OF_LIBFDT 1
55
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040056/*
57 * NS16550 Configuration
58 */
59
60#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
61
62#define CONFIG_SYS_NS16550
63#define CONFIG_SYS_NS16550_SERIAL
64#define CONFIG_SYS_NS16550_REG_SIZE (-4)
65#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
66
67/* select serial console configuration */
68#define CONFIG_CONS_INDEX 3
69#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
70#define CONFIG_SERIAL3 3
71
72/* allow to overwrite serial and ethaddr */
73#define CONFIG_ENV_OVERWRITE
74#define CONFIG_BAUDRATE 115200
75#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
Enric Balletbo i Serraf49d7b62010-11-04 15:34:33 -040076#define CONFIG_GENERIC_MMC 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040077#define CONFIG_MMC 1
Enric Balletbo i Serraf49d7b62010-11-04 15:34:33 -040078#define CONFIG_OMAP_HSMMC 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040079#define CONFIG_DOS_PARTITION 1
80
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040081/* USB */
82#define CONFIG_MUSB_UDC 1
83#define CONFIG_USB_OMAP3 1
84#define CONFIG_TWL4030_USB 1
85
86/* USB device configuration */
87#define CONFIG_USB_DEVICE 1
88#define CONFIG_USB_TTY 1
89#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
90
91/* Change these to suit your needs */
92#define CONFIG_USBD_VENDORID 0x0451
93#define CONFIG_USBD_PRODUCTID 0x5678
94#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
95#define CONFIG_USBD_PRODUCT_NAME "IGEP"
96
97/* commands to include */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_CACHE
101#define CONFIG_CMD_EXT2 /* EXT2 Support */
102#define CONFIG_CMD_FAT /* FAT support */
103#define CONFIG_CMD_I2C /* I2C serial bus support */
104#define CONFIG_CMD_MMC /* MMC support */
105#define CONFIG_CMD_ONENAND /* ONENAND support */
106#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
107#define CONFIG_CMD_DHCP
108#define CONFIG_CMD_PING
109#define CONFIG_CMD_NFS /* NFS support */
110#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
111#define CONFIG_MTD_DEVICE
112
113#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
114#undef CONFIG_CMD_IMLS /* List all found images */
115
116#define CONFIG_SYS_NO_FLASH
117#define CONFIG_HARD_I2C 1
118#define CONFIG_SYS_I2C_SPEED 100000
119#define CONFIG_SYS_I2C_SLAVE 1
120#define CONFIG_SYS_I2C_BUS 0
121#define CONFIG_SYS_I2C_BUS_SELECT 1
122#define CONFIG_DRIVER_OMAP34XX_I2C 1
123
124/*
125 * TWL4030
126 */
127#define CONFIG_TWL4030_POWER 1
128
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400129#define CONFIG_BOOTDELAY 3
130
131#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -0400132 "usbtty=cdc_acm\0" \
133 "loadaddr=0x82000000\0" \
134 "usbtty=cdc_acm\0" \
135 "console=ttyS2,115200n8\0" \
136 "mpurate=500\0" \
137 "vram=12M\0" \
138 "dvimode=1024x768MR-16@60\0" \
139 "defaultdisplay=dvi\0" \
140 "mmcdev=0\0" \
141 "mmcroot=/dev/mmcblk0p2 rw\0" \
142 "mmcrootfstype=ext3 rootwait\0" \
143 "nandroot=/dev/mtdblock4 rw\0" \
144 "nandrootfstype=jffs2\0" \
145 "mmcargs=setenv bootargs console=${console} " \
146 "mpurate=${mpurate} " \
147 "vram=${vram} " \
148 "omapfb.mode=dvi:${dvimode} " \
149 "omapfb.debug=y " \
150 "omapdss.def_disp=${defaultdisplay} " \
151 "root=${mmcroot} " \
152 "rootfstype=${mmcrootfstype}\0" \
153 "nandargs=setenv bootargs console=${console} " \
154 "mpurate=${mpurate} " \
155 "vram=${vram} " \
156 "omapfb.mode=dvi:${dvimode} " \
157 "omapfb.debug=y " \
158 "omapdss.def_disp=${defaultdisplay} " \
159 "root=${nandroot} " \
160 "rootfstype=${nandrootfstype}\0" \
161 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
162 "bootscript=echo Running bootscript from mmc ...; " \
163 "source ${loadaddr}\0" \
164 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
165 "mmcboot=echo Booting from mmc ...; " \
166 "run mmcargs; " \
167 "bootm ${loadaddr}\0" \
168 "nandboot=echo Booting from onenand ...; " \
169 "run nandargs; " \
170 "onenand read ${loadaddr} 280000 400000; " \
171 "bootm ${loadaddr}\0" \
172
173#define CONFIG_BOOTCOMMAND \
174 "if mmc rescan ${mmcdev}; then " \
175 "if run loadbootscript; then " \
176 "run bootscript; " \
177 "else " \
178 "if run loaduimage; then " \
179 "run mmcboot; " \
180 "else run nandboot; " \
181 "fi; " \
182 "fi; " \
183 "else run nandboot; fi"
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400184
185#define CONFIG_AUTO_COMPLETE 1
186
187/*
188 * Miscellaneous configurable options
189 */
190#define CONFIG_SYS_LONGHELP /* undef to save memory */
191#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
192#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
193#define CONFIG_SYS_PROMPT "U-Boot # "
194#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
195/* Print Buffer Size */
196#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
197 sizeof(CONFIG_SYS_PROMPT) + 16)
198#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
199/* Boot Argument Buffer Size */
200#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
201
202#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
203 /* works on */
204#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
205 0x01F00000) /* 31MB */
206
207#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
208 /* load address */
209
210#define CONFIG_SYS_MONITOR_LEN (256 << 10)
211
212/*
213 * OMAP3 has 12 GP timers, they can be driven by the system clock
214 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
215 * This rate is divided by a local divisor.
216 */
217#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
218#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
219#define CONFIG_SYS_HZ 1000
220
221/*
222 * Stack sizes
223 *
224 * The stack sizes are set up in start.S using the settings below
225 */
226#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
227
228/*
229 * Physical Memory Map
230 *
231 */
232#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
233#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
234#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */
235#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
236
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400237/*
238 * FLASH and environment organization
239 */
240
241#define PISMO1_ONEN_SIZE GPMC_SIZE_128M /* Configure the PISMO */
242
243#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
244
245#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
246
247#define CONFIG_ENV_IS_IN_ONENAND 1
248#define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */
249#define CONFIG_ENV_ADDR ONENAND_ENV_OFFSET
250
251/*
252 * Size of malloc() pool
253 */
254#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400255
256/*
257 * SMSC911x Ethernet
258 */
259#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400260#define CONFIG_SMC911X
261#define CONFIG_SMC911X_32_BIT
262#define CONFIG_SMC911X_BASE 0x2C000000
263#endif /* (CONFIG_CMD_NET) */
264
265#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Steve Sakoman31bfcf12010-10-27 05:04:30 -0700266#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
267#define CONFIG_SYS_INIT_RAM_SIZE 0x800
268#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
269 CONFIG_SYS_INIT_RAM_SIZE - \
270 GENERATED_GBL_DATA_SIZE)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -0400271
272#endif /* __CONFIG_H */