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Cyril Chemparathy2b629972012-07-24 12:22:16 +00001/*
2 * CPSW Ethernet Switch Driver
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef _CPSW_H_
17#define _CPSW_H_
18
Grygorii Strashko62f8e842019-09-19 11:16:42 +030019#include <dm/ofnode.h>
20
Faiz Abbas0229c932019-03-18 13:54:37 +053021/* reg offset */
22#define CPSW_HOST_PORT_OFFSET 0x108
23#define CPSW_SLAVE0_OFFSET 0x208
24#define CPSW_SLAVE1_OFFSET 0x308
25#define CPSW_SLAVE_SIZE 0x100
26#define CPSW_CPDMA_OFFSET 0x800
27#define CPSW_HW_STATS 0x900
28#define CPSW_STATERAM_OFFSET 0xa00
29#define CPSW_CPTS_OFFSET 0xc00
30#define CPSW_ALE_OFFSET 0xd00
31#define CPSW_SLIVER0_OFFSET 0xd80
32#define CPSW_SLIVER1_OFFSET 0xdc0
33#define CPSW_BD_OFFSET 0x2000
34#define CPSW_MDIO_DIV 0xff
35
36#define AM335X_GMII_SEL_OFFSET 0x630
37
Cyril Chemparathy2b629972012-07-24 12:22:16 +000038struct cpsw_slave_data {
39 u32 slave_reg_ofs;
40 u32 sliver_reg_ofs;
Mugunthan V N9c653aa2014-02-18 07:31:52 -050041 int phy_addr;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000042 int phy_if;
Grygorii Strashko62f8e842019-09-19 11:16:42 +030043 ofnode phy_of_handle;
Grygorii Strashko3c57b622019-09-19 11:16:39 +030044 int max_speed;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000045};
46
47enum {
48 CPSW_CTRL_VERSION_1 = 0,
49 CPSW_CTRL_VERSION_2 /* am33xx like devices */
50};
51
52struct cpsw_platform_data {
53 u32 mdio_base;
54 u32 cpsw_base;
Mugunthan V N4cc77892015-09-07 14:22:21 +053055 u32 mac_id;
56 u32 gmii_sel;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000057 int mdio_div;
58 int channels; /* number of cpdma channels (symmetric) */
59 u32 cpdma_reg_ofs; /* cpdma register offset */
60 int slaves; /* number of slave cpgmac ports */
61 u32 ale_reg_ofs; /* address lookup engine reg offset */
62 int ale_entries; /* ale table size */
63 u32 host_port_reg_ofs; /* cpdma host port registers */
64 u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
Mugunthan V N2bf36ac2013-07-08 16:04:37 +053065 u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */
Cyril Chemparathy2b629972012-07-24 12:22:16 +000066 u32 mac_control;
67 struct cpsw_slave_data *slave_data;
68 void (*control)(int enabled);
69 u32 host_port_num;
Mugunthan V N7a022752014-05-22 14:37:10 +053070 u32 active_slave;
Mugunthan V Nab971532016-10-13 19:33:38 +053071 bool rmii_clock_external;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000072 u8 version;
Faiz Abbase50f8782019-03-18 13:54:32 +053073 const char *phy_sel_compat;
Faiz Abbasa58d2222019-03-18 13:54:34 +053074 u32 syscon_addr;
75 const char *macid_sel_compat;
Cyril Chemparathy2b629972012-07-24 12:22:16 +000076};
77
78int cpsw_register(struct cpsw_platform_data *data);
Faiz Abbasa58d2222019-03-18 13:54:34 +053079int ti_cm_get_macid_addr(struct udevice *dev, int slave,
80 struct cpsw_platform_data *data);
81void ti_cm_get_macid(struct udevice *dev, struct cpsw_platform_data *data,
82 u8 *mac_addr);
Sekhar Norie2597be2018-08-23 17:11:29 +053083int cpsw_get_slave_phy_addr(struct udevice *dev, int slave);
Cyril Chemparathy2b629972012-07-24 12:22:16 +000084
85#endif /* _CPSW_H_ */