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wdenkc15f3122004-10-10 22:44:24 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8540 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/* mpc8560ads board configuration file */
28/* please refer to doc/README.mpc85xx for more info */
29/* make sure you change the MAC address and other network params first,
30 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
31 */
wdenk8b74bf32004-10-11 23:10:30 +000032
wdenkc15f3122004-10-10 22:44:24 +000033#ifndef __CONFIG_H
34#define __CONFIG_H
35
36#if XXX
37#define DEBUG /* General debug */
38#define ET_DEBUG
39#endif
40#define TSEC_DEBUG
41
42/* High Level Configuration Options */
43#define CONFIG_BOOKE 1 /* BOOKE */
44#define CONFIG_E500 1 /* BOOKE e500 family */
45#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
46#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
47
48
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050049#define CONFIG_CPM2 1 /* has CPM2 */
wdenkc15f3122004-10-10 22:44:24 +000050
51#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
52
53#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
54
55#define CONFIG_TSEC_ENET /* tsec ethernet support */
56#undef CONFIG_PCI /* pci ethernet support */
57#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
58
59
60#define CONFIG_ENV_OVERWRITE
61
62/* Using Localbus SDRAM to emulate flash before we can program the flash,
63 * normally you need a flash-boot image(u-boot.bin), if so undef this.
64 */
65#undef CONFIG_RAM_AS_FLASH
66
67#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
68 #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
69#else
70 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
71#endif
72
73/* below can be toggled for performance analysis. otherwise use default */
74#define CONFIG_L2_CACHE /* toggle L2 cache */
75#undef CONFIG_BTB /* toggle branch predition */
76#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
77
78#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
79
80#undef CFG_DRAM_TEST /* memory test, takes time */
81#define CFG_MEMTEST_START 0x00200000 /* memtest region */
82#define CFG_MEMTEST_END 0x00400000
83
84#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
85 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
86 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
87#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
88#endif
89
90/*
91 * Base addresses -- Note these are effective addresses where the
92 * actual resources get mapped (not physical addresses)
93 */
94#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
95
96#if XXX
97 #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
98#else
99 #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */
100#endif
101#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
102
103#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
104#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
105#define CFG_SDRAM_SIZE 512 /* DDR is 512MB */
106#define SPD_EEPROM_ADDRESS 0x55 /* DDR DIMM */
107
108#undef CONFIG_DDR_ECC /* only for ECC DDR module */
109#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
110
111#if defined(CONFIG_MPC85xx_REV1)
112 #define CONFIG_DDR_DLL /* possible DLL fix needed */
113#endif
114
115#undef CONFIG_CLOCKS_IN_MHZ
116
117#if defined(CONFIG_RAM_AS_FLASH)
118 #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
119 #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
120 #define CFG_BR0_PRELIM 0xf8000801 /* port size 8bit */
121 #define CFG_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
122#else /* Boot from real Flash */
123 #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
124 #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
125 #define CFG_BR0_PRELIM 0xff800801 /* port size 8bit */
126 #define CFG_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
127#endif
128#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
129
130/* local bus definitions */
131#define CFG_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
132#define CFG_OR1_PRELIM 0xfc000ff7
133
134#define CFG_BR2_PRELIM 0x00000000 /* CS2 not used */
135#define CFG_OR2_PRELIM 0x00000000
136
137#define CFG_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
138#define CFG_OR3_PRELIM 0xfc000cc1
139
140#if defined(CONFIG_RAM_AS_FLASH)
141 #define CFG_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
142#else
143 #define CFG_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
144#endif
145#define CFG_OR4_PRELIM 0xfc000cc1
146
147#define CFG_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
148#if 1
149 #define CFG_OR5_PRELIM 0xff000ff7
150#else
151 #define CFG_OR5_PRELIM 0xff0000f0
152#endif
153
154#define CFG_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
155#define CFG_OR6_PRELIM 0xfc000ff7
156#define CFG_LBC_LCRR 0x00030002 /* local bus freq */
157#define CFG_LBC_LBCR 0x00000000
158#define CFG_LBC_LSRT 0x20000000
159#define CFG_LBC_MRTPR 0x20000000
160#define CFG_LBC_LSDMR_1 0x2861b723
161#define CFG_LBC_LSDMR_2 0x0861b723
162#define CFG_LBC_LSDMR_3 0x0861b723
163#define CFG_LBC_LSDMR_4 0x1861b723
164#define CFG_LBC_LSDMR_5 0x4061b723
165
166/* just hijack the MOT BCSR def for SBC8560 misc devices */
167#define CFG_BCSR ((CFG_BR5_PRELIM & 0xff000000)|0x00400000)
168/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
169
170#define CONFIG_L1_INIT_RAM
171#define CFG_INIT_RAM_LOCK 1
172#define CFG_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
173#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
174
175#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
176#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
177#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
178
179#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
180#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
181
182/* Serial Port */
183#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
184#undef CONFIG_CONS_NONE /* define if console on something else */
185
186#define CONFIG_CONS_INDEX 1
187#undef CONFIG_SERIAL_SOFTWARE_FIFO
188#define CFG_NS16550
189#define CFG_NS16550_SERIAL
190#define CFG_NS16550_REG_SIZE 1
191#if 0
192#define CFG_NS16550_CLK 1843200 /* get_bus_freq(0) */
193#else
194#define CFG_NS16550_CLK 264000000 /* get_bus_freq(0) */
195#endif
196
197#define CONFIG_BAUDRATE 9600
198
199#define CFG_BAUDRATE_TABLE \
200 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
201
202#if 0
203#define CFG_NS16550_COM1 ((CFG_BR5_PRELIM & 0xff000000)+0x00700000)
204#define CFG_NS16550_COM2 ((CFG_BR5_PRELIM & 0xff000000)+0x00800000)
205#else
wdenk8b74bf32004-10-11 23:10:30 +0000206/* SBC8540 uses internal COMM controller */
wdenkc15f3122004-10-10 22:44:24 +0000207#define CFG_NS16550_COM1 ((CFG_CCSRBAR & 0xfff00000)+0x00004500)
208#define CFG_NS16550_COM2 ((CFG_CCSRBAR & 0xfff00000)+0x00004600)
209#endif
210
211/* Use the HUSH parser */
212#define CFG_HUSH_PARSER
213#ifdef CFG_HUSH_PARSER
214#define CFG_PROMPT_HUSH_PS2 "> "
215#endif
216
Jon Loeliger20476722006-10-20 15:50:15 -0500217/*
218 * I2C
219 */
220#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
221#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenkc15f3122004-10-10 22:44:24 +0000222#undef CONFIG_SOFT_I2C /* I2C bit-banged */
223#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
224#define CFG_I2C_SLAVE 0x7F
225#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500226#define CFG_I2C_OFFSET 0x3000
wdenkc15f3122004-10-10 22:44:24 +0000227
228#define CFG_PCI_MEM_BASE 0xC0000000
229#define CFG_PCI_MEM_PHYS 0xC0000000
230#define CFG_PCI_MEM_SIZE 0x10000000
231
232#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
233
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500234# define CONFIG_NET_MULTI 1
235# define CONFIG_MPC85xx_TSEC1
236# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
237# define CONFIG_MII 1 /* MII PHY management */
238# define TSEC1_PHY_ADDR 25
239# define TSEC1_PHYIDX 0
240/* Options are: TSEC0 */
241# define CONFIG_ETHPRIME "TSEC0"
wdenkc15f3122004-10-10 22:44:24 +0000242
wdenk8b74bf32004-10-11 23:10:30 +0000243
wdenkc15f3122004-10-10 22:44:24 +0000244#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
245
246 #undef CONFIG_ETHER_NONE /* define if ether on something else */
247 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
248 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk8b74bf32004-10-11 23:10:30 +0000249
wdenkc15f3122004-10-10 22:44:24 +0000250 #if (CONFIG_ETHER_INDEX == 2)
251 /*
252 * - Rx-CLK is CLK13
253 * - Tx-CLK is CLK14
254 * - Select bus for bd/buffers
255 * - Full duplex
256 */
257 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
258 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
259 #define CFG_CPMFCR_RAMTYPE 0
260 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
wdenk8b74bf32004-10-11 23:10:30 +0000261
wdenkc15f3122004-10-10 22:44:24 +0000262 #elif (CONFIG_ETHER_INDEX == 3)
263 /* need more definitions here for FE3 */
264 #endif /* CONFIG_ETHER_INDEX */
wdenk8b74bf32004-10-11 23:10:30 +0000265
wdenkc15f3122004-10-10 22:44:24 +0000266 #define CONFIG_MII /* MII PHY management */
267 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
268 /*
269 * GPIO pins used for bit-banged MII communications
270 */
271 #define MDIO_PORT 2 /* Port C */
272 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
273 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
274 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
275
276 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
277 else iop->pdat &= ~0x00400000
278
279 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
280 else iop->pdat &= ~0x00200000
281
282 #define MIIDELAY udelay(1)
wdenk8b74bf32004-10-11 23:10:30 +0000283
wdenkc15f3122004-10-10 22:44:24 +0000284#endif
285
286/*-----------------------------------------------------------------------
287 * FLASH and environment organization
288 */
289
290#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
291#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
292#if 0
293#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
294#define CFG_FLASH_PROTECTION /* use hardware protection */
295#endif
296#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
297#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
298
299#undef CFG_FLASH_CHECKSUM
300#define CFG_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
301#define CFG_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
302
303#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
304
305#if 0
306/* XXX This doesn't work and I don't want to fix it */
307#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
308 #define CFG_RAMBOOT
309#else
310 #undef CFG_RAMBOOT
311#endif
312#endif
313
314/* Environment */
315#if !defined(CFG_RAMBOOT)
316 #if defined(CONFIG_RAM_AS_FLASH)
317 #define CFG_ENV_IS_NOWHERE
318 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
319 #define CFG_ENV_SIZE 0x2000
320 #else
321 #define CFG_ENV_IS_IN_FLASH 1
322 #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
323 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
324 #define CFG_ENV_SIZE 0x2000 /* CFG_ENV_SECT_SIZE */
325 #endif
326#else
327 #define CFG_NO_FLASH 1 /* Flash is not usable now */
328 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
329 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
330 #define CFG_ENV_SIZE 0x2000
331#endif
332
333#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
334/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
335#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
336#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
337
338#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
339#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
340
341#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
342 #if defined(CONFIG_PCI)
343 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
344 CFG_CMD_PING | CFG_CMD_I2C) & \
345 ~(CFG_CMD_ENV | \
346 CFG_CMD_LOADS ))
347 #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
348 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
349 CFG_CMD_PING | CFG_CMD_I2C) & \
350 ~(CFG_CMD_ENV))
351 #endif
352#else
353 #if defined(CONFIG_PCI)
354 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
355 CFG_CMD_PING | CFG_CMD_I2C)
356 #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC))
357 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
358 CFG_CMD_PING | CFG_CMD_I2C)
359 #endif
360#endif
361
362#include <cmd_confdefs.h>
363
364#undef CONFIG_WATCHDOG /* watchdog disabled */
365
366/*
367 * Miscellaneous configurable options
368 */
369#define CFG_LONGHELP /* undef to save memory */
370#define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */
371#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
372 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
373#else
374 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
375#endif
376#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
377#define CFG_MAXARGS 16 /* max number of command args */
378#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
379#define CFG_LOAD_ADDR 0x1000000 /* default load address */
380#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
381
382/*
383 * For booting Linux, the board info and command line data
384 * have to be in the first 8 MB of memory, since this is
385 * the maximum mapped by the Linux kernel during initialization.
386 */
387#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
388
389/* Cache Configuration */
390#define CFG_DCACHE_SIZE 32768
391#define CFG_CACHELINE_SIZE 32
392#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
393 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
394#endif
395
396/*
397 * Internal Definitions
398 *
399 * Boot Flags
400 */
401#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
402#define BOOTFLAG_WARM 0x02 /* Software reboot */
403
404#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
405 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
406 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
407#endif
408
409/*Note: change below for your network setting!!! */
410#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000411# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
412# define CONFIG_HAS_ETH1
413# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
414# define CONFIG_HAS_ETH2
415# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
wdenkc15f3122004-10-10 22:44:24 +0000416#endif
417
418#define CONFIG_SERVERIP YourServerIP
419#define CONFIG_IPADDR YourTargetIP
420#define CONFIG_GATEWAYIP YourGatewayIP
421#define CONFIG_NETMASK 255.255.255.0
422#define CONFIG_HOSTNAME SBC8560
423#define CONFIG_ROOTPATH YourRootPath
424#define CONFIG_BOOTFILE YourImageName
425
426#endif /* __CONFIG_H */