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Tom Warren3f82b1d2011-01-27 10:58:05 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ns16550.h>
26#include <asm/io.h>
27#include <asm/arch/tegra2.h>
28#include <asm/arch/sys_proto.h>
29
30#include <asm/arch/clk_rst.h>
Simon Glassb4ba2be2011-08-30 06:23:13 +000031#include <asm/arch/clock.h>
Tom Warren3f82b1d2011-01-27 10:58:05 +000032#include <asm/arch/pinmux.h>
33#include <asm/arch/uart.h>
Tom Warren74652cf2011-04-14 12:18:06 +000034#include "board.h"
Tom Warren3f82b1d2011-01-27 10:58:05 +000035
Tom Warren21ef6a12011-05-31 10:30:37 +000036#ifdef CONFIG_TEGRA2_MMC
37#include <mmc.h>
38#endif
39
Tom Warren3f82b1d2011-01-27 10:58:05 +000040DECLARE_GLOBAL_DATA_PTR;
41
42const struct tegra2_sysinfo sysinfo = {
43 CONFIG_TEGRA2_BOARD_STRING
44};
45
46/*
47 * Routine: timer_init
48 * Description: init the timestamp and lastinc value
49 */
50int timer_init(void)
51{
Tom Warren3f82b1d2011-01-27 10:58:05 +000052 return 0;
53}
54
Simon Glass4ed59e72011-09-21 12:40:04 +000055static void enable_uart(enum periph_id pid)
56{
57 /* Assert UART reset and enable clock */
58 reset_set_enable(pid, 1);
59 clock_enable(pid);
60 clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
61
62 /* wait for 2us */
63 udelay(2);
64
65 /* De-assert reset to UART */
66 reset_set_enable(pid, 0);
67}
68
Tom Warren3f82b1d2011-01-27 10:58:05 +000069/*
70 * Routine: clock_init_uart
71 * Description: init the PLL and clock for the UART(s)
72 */
73static void clock_init_uart(void)
74{
Tom Warren3f82b1d2011-01-27 10:58:05 +000075#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
Simon Glass4ed59e72011-09-21 12:40:04 +000076 enable_uart(PERIPH_ID_UART1);
Tom Warren3f82b1d2011-01-27 10:58:05 +000077#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
78#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
Simon Glass4ed59e72011-09-21 12:40:04 +000079 enable_uart(PERIPH_ID_UART4);
Tom Warren3f82b1d2011-01-27 10:58:05 +000080#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
81}
82
83/*
84 * Routine: pin_mux_uart
85 * Description: setup the pin muxes/tristate values for the UART(s)
86 */
87static void pin_mux_uart(void)
88{
Tom Warren3f82b1d2011-01-27 10:58:05 +000089#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
Simon Glass20e18e02011-09-21 12:40:06 +000090 pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
91 pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
Tom Warren3f82b1d2011-01-27 10:58:05 +000092
Simon Glassc3cf49d2011-09-21 12:40:05 +000093 pinmux_tristate_disable(PINGRP_IRRX);
94 pinmux_tristate_disable(PINGRP_IRTX);
Tom Warren3f82b1d2011-01-27 10:58:05 +000095#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
96#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
Simon Glass20e18e02011-09-21 12:40:06 +000097 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
Tom Warren3f82b1d2011-01-27 10:58:05 +000098
Simon Glassc3cf49d2011-09-21 12:40:05 +000099 pinmux_tristate_disable(PINGRP_GMC);
Tom Warren3f82b1d2011-01-27 10:58:05 +0000100#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
101}
102
Simon Glass3e00dbd2011-09-21 12:40:03 +0000103#ifdef CONFIG_TEGRA2_MMC
Tom Warren3f82b1d2011-01-27 10:58:05 +0000104/*
Tom Warren21ef6a12011-05-31 10:30:37 +0000105 * Routine: clock_init_mmc
106 * Description: init the PLL and clocks for the SDMMC controllers
107 */
108static void clock_init_mmc(void)
109{
Simon Glass4ed59e72011-09-21 12:40:04 +0000110 clock_start_periph_pll(PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH, 20000000);
111 clock_start_periph_pll(PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH, 20000000);
Tom Warren21ef6a12011-05-31 10:30:37 +0000112}
113
114/*
115 * Routine: pin_mux_mmc
116 * Description: setup the pin muxes/tristate values for the SDMMC(s)
117 */
118static void pin_mux_mmc(void)
119{
Simon Glass20e18e02011-09-21 12:40:06 +0000120 /* SDMMC4: config 3, x8 on 2nd set of pins */
121 pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
122 pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
123 pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
Tom Warren21ef6a12011-05-31 10:30:37 +0000124
Simon Glassc3cf49d2011-09-21 12:40:05 +0000125 pinmux_tristate_disable(PINGRP_ATB);
126 pinmux_tristate_disable(PINGRP_GMA);
127 pinmux_tristate_disable(PINGRP_GME);
Tom Warren21ef6a12011-05-31 10:30:37 +0000128
Simon Glass20e18e02011-09-21 12:40:06 +0000129 /* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
130 pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
131 pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
132 pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
Tom Warren21ef6a12011-05-31 10:30:37 +0000133
Simon Glassc3cf49d2011-09-21 12:40:05 +0000134 pinmux_tristate_disable(PINGRP_SDC);
135 pinmux_tristate_disable(PINGRP_SDD);
136 pinmux_tristate_disable(PINGRP_SDB);
Tom Warren21ef6a12011-05-31 10:30:37 +0000137}
Simon Glass3e00dbd2011-09-21 12:40:03 +0000138#endif
Tom Warrenf4ef6662011-04-14 12:09:41 +0000139
140/*
Tom Warren3f82b1d2011-01-27 10:58:05 +0000141 * Routine: board_init
142 * Description: Early hardware init.
143 */
144int board_init(void)
145{
Simon Glass4ed59e72011-09-21 12:40:04 +0000146 clock_init();
147 clock_verify();
148
Tom Warren3f82b1d2011-01-27 10:58:05 +0000149 /* boot param addr */
150 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
Tom Warren3f82b1d2011-01-27 10:58:05 +0000151
Tom Warren3f82b1d2011-01-27 10:58:05 +0000152 return 0;
153}
Tom Warren21ef6a12011-05-31 10:30:37 +0000154
155#ifdef CONFIG_TEGRA2_MMC
156/* this is a weak define that we are overriding */
157int board_mmc_init(bd_t *bd)
158{
159 debug("board_mmc_init called\n");
160 /* Enable clocks, muxes, etc. for SDMMC controllers */
161 clock_init_mmc();
162 pin_mux_mmc();
163
164 debug("board_mmc_init: init eMMC\n");
165 /* init dev 0, eMMC chip, with 4-bit bus */
166 tegra2_mmc_init(0, 4);
167
168 debug("board_mmc_init: init SD slot\n");
169 /* init dev 1, SD slot, with 4-bit bus */
170 tegra2_mmc_init(1, 4);
171
172 return 0;
173}
174
175/* this is a weak define that we are overriding */
176int board_mmc_getcd(u8 *cd, struct mmc *mmc)
177{
178 debug("board_mmc_getcd called\n");
179 /*
180 * Hard-code CD presence for now. Need to add GPIO inputs
181 * for Seaboard & Harmony (& Kaen/Aebl/Wario?)
182 */
183 *cd = 1;
184 return 0;
185}
186#endif
Simon Glass3e00dbd2011-09-21 12:40:03 +0000187
188#ifdef CONFIG_BOARD_EARLY_INIT_F
189int board_early_init_f(void)
190{
Simon Glass4ed59e72011-09-21 12:40:04 +0000191 /* Initialize essential common plls */
192 clock_early_init();
193
Simon Glass3e00dbd2011-09-21 12:40:03 +0000194 /* Initialize UART clocks */
195 clock_init_uart();
196
197 /* Initialize periph pinmuxes */
198 pin_mux_uart();
199
200 /* Initialize periph GPIOs */
201 gpio_config_uart();
202
203 /* Init UART, scratch regs, and start CPU */
204 tegra2_start();
205 return 0;
206}
207#endif /* EARLY_INIT */