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Lokesh Vutlaea8ad1d2018-08-27 15:59:08 +05301// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for AM6 SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
Sekhar Nori476e9912019-08-01 19:13:00 +05308#include <dt-bindings/phy/phy-am654-serdes.h>
9#include <dt-bindings/phy/phy.h>
10
Lokesh Vutlaea8ad1d2018-08-27 15:59:08 +053011&cbass_main {
12 gic500: interrupt-controller@1800000 {
13 compatible = "arm,gic-v3";
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053014 #address-cells = <2>;
15 #size-cells = <2>;
Lokesh Vutlaea8ad1d2018-08-27 15:59:08 +053016 ranges;
17 #interrupt-cells = <3>;
18 interrupt-controller;
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053019 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0x90000>; /* GICR */
Lokesh Vutlaea8ad1d2018-08-27 15:59:08 +053021 /*
22 * vcpumntirq:
23 * virtual CPU interface maintenance interrupt
24 */
25 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
26
27 gic_its: gic-its@18200000 {
28 compatible = "arm,gic-v3-its";
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053029 reg = <0x00 0x01820000 0x00 0x10000>;
Lokesh Vutlaea8ad1d2018-08-27 15:59:08 +053030 msi-controller;
31 #msi-cells = <1>;
32 };
33 };
Lokesh Vutla2d0eba32018-11-02 19:51:08 +053034
35 secure_proxy_main: mailbox@32c00000 {
36 compatible = "ti,am654-secure-proxy";
37 #mbox-cells = <1>;
38 reg-names = "target_data", "rt", "scfg";
39 reg = <0x00 0x32c00000 0x00 0x100000>,
40 <0x00 0x32400000 0x00 0x100000>,
41 <0x00 0x32800000 0x00 0x100000>;
42 interrupt-names = "rx_011";
43 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
44 };
45
46 main_uart0: serial@2800000 {
47 compatible = "ti,am654-uart";
48 reg = <0x00 0x02800000 0x00 0x100>;
49 reg-shift = <2>;
50 reg-io-width = <4>;
51 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
52 clock-frequency = <48000000>;
53 current-speed = <115200>;
54 };
55
56 main_uart1: serial@2810000 {
57 compatible = "ti,am654-uart";
58 reg = <0x00 0x02810000 0x00 0x100>;
59 reg-shift = <2>;
60 reg-io-width = <4>;
61 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
62 clock-frequency = <48000000>;
63 current-speed = <115200>;
64 };
65
66 main_uart2: serial@2820000 {
67 compatible = "ti,am654-uart";
68 reg = <0x00 0x02820000 0x00 0x100>;
69 reg-shift = <2>;
70 reg-io-width = <4>;
71 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
72 clock-frequency = <48000000>;
73 current-speed = <115200>;
74 };
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053075
76 main_pmx0: pinmux@11c000 {
77 compatible = "pinctrl-single";
78 reg = <0x0 0x11c000 0x0 0x2e4>;
79 #pinctrl-cells = <1>;
80 pinctrl-single,register-width = <32>;
81 pinctrl-single,function-mask = <0xffffffff>;
82 };
83
Andreas Dannenberg9bbdfdf2019-06-04 18:08:13 -050084 main_pmx1: pinmux@11c2e8 {
85 compatible = "pinctrl-single";
86 reg = <0x0 0x11c2e8 0x0 0x24>;
87 #pinctrl-cells = <1>;
88 pinctrl-single,register-width = <32>;
89 pinctrl-single,function-mask = <0xffffffff>;
90 };
91
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053092 sdhci0: sdhci@4f80000 {
93 compatible = "ti,am654-sdhci-5.1";
94 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
Lokesh Vutla355be912019-06-07 19:24:47 +053095 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +053096 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
97 clock-names = "clk_ahb", "clk_xin";
98 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
99 mmc-ddr-1_8v;
100 mmc-hs200-1_8v;
Faiz Abbasc7d106b2020-02-26 13:44:33 +0530101 ti,otap-del-sel-legacy = <0x0>;
102 ti,otap-del-sel-mmc-hs = <0x0>;
103 ti,otap-del-sel-sd-hs = <0x0>;
104 ti,otap-del-sel-sdr12 = <0x0>;
105 ti,otap-del-sel-sdr25 = <0x0>;
106 ti,otap-del-sel-sdr50 = <0x8>;
107 ti,otap-del-sel-sdr104 = <0x5>;
108 ti,otap-del-sel-ddr50 = <0x5>;
109 ti,otap-del-sel-ddr52 = <0x5>;
110 ti,otap-del-sel-hs200 = <0x5>;
111 ti,otap-del-sel-hs400 = <0x0>;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530112 ti,trm-icp = <0x8>;
113 dma-coherent;
114 };
Andreas Dannenbergbbe59162019-06-04 18:08:14 -0500115
Faiz Abbas2121c7e2021-02-04 15:10:56 +0530116 sdhci1: sdhci@4fa0000 {
117 compatible = "ti,am654-sdhci-5.1";
118 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
119 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
120 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
121 clock-names = "clk_ahb", "clk_xin";
122 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
123 ti,otap-del-sel-legacy = <0x0>;
124 ti,otap-del-sel-mmc-hs = <0x0>;
125 ti,otap-del-sel-sd-hs = <0x0>;
126 ti,otap-del-sel-sdr12 = <0x0>;
127 ti,otap-del-sel-sdr25 = <0x0>;
128 ti,otap-del-sel-sdr50 = <0x8>;
129 ti,otap-del-sel-sdr104 = <0x7>;
130 ti,otap-del-sel-ddr50 = <0x4>;
131 ti,otap-del-sel-ddr52 = <0x4>;
132 ti,otap-del-sel-hs200 = <0x7>;
133 ti,clkbuf-sel = <0x7>;
134 ti,trm-icp = <0x8>;
135 dma-coherent;
136 };
137
Andreas Dannenbergbbe59162019-06-04 18:08:14 -0500138 main_i2c0: i2c@2000000 {
139 compatible = "ti,am654-i2c", "ti,omap4-i2c";
140 reg = <0x0 0x2000000 0x0 0x100>;
141 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 clock-names = "fck";
145 clocks = <&k3_clks 110 1>;
Lokesh Vutla355be912019-06-07 19:24:47 +0530146 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenbergbbe59162019-06-04 18:08:14 -0500147 };
148
149 main_i2c1: i2c@2010000 {
150 compatible = "ti,am654-i2c", "ti,omap4-i2c";
151 reg = <0x0 0x2010000 0x0 0x100>;
152 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
153 #address-cells = <1>;
154 #size-cells = <0>;
155 clock-names = "fck";
156 clocks = <&k3_clks 111 1>;
Lokesh Vutla355be912019-06-07 19:24:47 +0530157 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenbergbbe59162019-06-04 18:08:14 -0500158 };
159
160 main_i2c2: i2c@2020000 {
161 compatible = "ti,am654-i2c", "ti,omap4-i2c";
162 reg = <0x0 0x2020000 0x0 0x100>;
163 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166 clock-names = "fck";
167 clocks = <&k3_clks 112 1>;
Lokesh Vutla355be912019-06-07 19:24:47 +0530168 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenbergbbe59162019-06-04 18:08:14 -0500169 };
170
171 main_i2c3: i2c@2030000 {
172 compatible = "ti,am654-i2c", "ti,omap4-i2c";
173 reg = <0x0 0x2030000 0x0 0x100>;
174 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 clock-names = "fck";
178 clocks = <&k3_clks 113 1>;
Lokesh Vutla355be912019-06-07 19:24:47 +0530179 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
Andreas Dannenbergbbe59162019-06-04 18:08:14 -0500180 };
Sekhar Nori476e9912019-08-01 19:13:00 +0530181
182 scm_conf: scm_conf@100000 {
183 compatible = "syscon", "simple-mfd";
184 reg = <0 0x00100000 0 0x1c000>;
185 #address-cells = <1>;
186 #size-cells = <1>;
187 ranges = <0x0 0x0 0x00100000 0x1c000>;
188
189 serdes_mux: mux-controller {
190 compatible = "mmio-mux";
191 #mux-control-cells = <1>;
192 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
193 <0x4090 0x3>; /* SERDES1 lane select */
194 };
195
196 pcie0_mode: pcie-mode@4060 {
197 compatible = "syscon";
198 reg = <0x00004060 0x4>;
199 };
200
201 pcie1_mode: pcie-mode@4070 {
202 compatible = "syscon";
203 reg = <0x00004070 0x4>;
204 };
205
206 serdes0_clk: serdes_clk@4080 {
207 compatible = "syscon";
208 reg = <0x00004080 0x4>;
209 };
210
211 serdes1_clk: serdes_clk@4090 {
212 compatible = "syscon";
213 reg = <0x00004090 0x4>;
214 };
215
216 pcie_devid: pcie-devid@210 {
217 compatible = "syscon";
218 reg = <0x00000210 0x4>;
219 };
220 };
221
222 serdes0: serdes@900000 {
223 compatible = "ti,phy-am654-serdes";
224 reg = <0x0 0x900000 0x0 0x2000>;
225 reg-names = "serdes";
226 #phy-cells = <2>;
227 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
228 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
229 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
230 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
231 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
232 ti,serdes-clk = <&serdes0_clk>;
233 mux-controls = <&serdes_mux 0>;
234 #clock-cells = <1>;
235 };
236
237 serdes1: serdes@910000 {
238 compatible = "ti,phy-am654-serdes";
239 reg = <0x0 0x910000 0x0 0x2000>;
240 reg-names = "serdes";
241 #phy-cells = <2>;
242 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
243 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
244 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
245 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
246 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
247 ti,serdes-clk = <&serdes1_clk>;
248 mux-controls = <&serdes_mux 1>;
249 #clock-cells = <1>;
250 };
251
252 pcie0_rc: pcie@5500000 {
253 compatible = "ti,am654-pcie-rc";
254 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
255 reg-names = "app", "dbics", "config", "atu";
256 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
257 #address-cells = <3>;
258 #size-cells = <2>;
259 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
260 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
261 ti,syscon-pcie-id = <&pcie_devid>;
262 ti,syscon-pcie-mode = <&pcie0_mode>;
263 bus-range = <0x0 0xff>;
264 status = "disabled";
265 device_type = "pci";
266 num-lanes = <1>;
267 num-ob-windows = <16>;
268 num-viewport = <16>;
269 max-link-speed = <3>;
270 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
271 #interrupt-cells = <1>;
272 interrupt-map-mask = <0 0 0 7>;
273 interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
274 <0 0 0 2 &pcie0_intc 0>, /* INT B */
275 <0 0 0 3 &pcie0_intc 0>, /* INT C */
276 <0 0 0 4 &pcie0_intc 0>; /* INT D */
277 msi-map = <0x0 &gic_its 0x0 0x10000>;
278
279 pcie0_intc: legacy-interrupt-controller@1 {
280 interrupt-controller;
281 #interrupt-cells = <1>;
282 interrupt-parent = <&gic500>;
283 interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
284 };
285 };
Vignesh Raghavendraa1ac85d2019-12-09 10:37:32 +0530286
287 dwc3_0: dwc3@4000000 {
288 compatible = "ti,am654-dwc3";
289 reg = <0x0 0x4000000 0x0 0x4000>;
290 #address-cells = <1>;
291 #size-cells = <1>;
292 ranges = <0x0 0x0 0x4000000 0x20000>;
293 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
294 dma-coherent;
295 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
296 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
297 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
298 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
299
300 usb0: usb@10000 {
301 compatible = "snps,dwc3";
302 reg = <0x10000 0x10000>;
303 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
306 interrupt-names = "peripheral",
307 "host",
308 "otg";
309 maximum-speed = "high-speed";
310 dr_mode = "otg";
311 phys = <&usb0_phy>;
312 phy-names = "usb2-phy";
313 snps,dis_u3_susphy_quirk;
314 };
315 };
316
317 usb0_phy: phy@4100000 {
318 compatible = "ti,am654-usb2", "ti,omap-usb2";
319 reg = <0x0 0x4100000 0x0 0x54>;
320 syscon-phy-power = <&scm_conf 0x4000>;
321 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
322 clock-names = "wkupclk", "refclk";
323 #phy-cells = <0>;
324 ti,dis-chg-det-quirk;
325 };
326
327 dwc3_1: dwc3@4020000 {
328 compatible = "ti,am654-dwc3";
329 reg = <0x0 0x4020000 0x0 0x4000>;
330 #address-cells = <1>;
331 #size-cells = <1>;
332 ranges = <0x0 0x0 0x4020000 0x20000>;
333 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
334 dma-coherent;
335 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
336 assigned-clocks = <&k3_clks 152 2>;
337 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
338
339 usb1: usb@10000 {
340 compatible = "snps,dwc3";
341 reg = <0x10000 0x10000>;
342 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
345 interrupt-names = "peripheral",
346 "host",
347 "otg";
348 maximum-speed = "high-speed";
349 dr_mode = "otg";
350 phys = <&usb1_phy>;
351 phy-names = "usb2-phy";
352 };
353 };
354
355 usb1_phy: phy@4110000 {
356 compatible = "ti,am654-usb2", "ti,omap-usb2";
357 reg = <0x0 0x4110000 0x0 0x54>;
358 syscon-phy-power = <&scm_conf 0x4020>;
359 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
360 clock-names = "wkupclk", "refclk";
361 #phy-cells = <0>;
362 ti,dis-chg-det-quirk;
363 };
Lokesh Vutlaea8ad1d2018-08-27 15:59:08 +0530364};