arch/arm/dts/bcm63138.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Broadcom BCM63138 DSL SoCs Device Tree
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "brcm,bcm63138", "brcm,bcmbca";
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0>;
			enable-method = "brcm,bcm63138";
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <1>;
			enable-method = "brcm,bcm63138";
		};
	};

	clocks {
		/* UBUS peripheral clock */
		periph_clk: periph_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
			clock-output-names = "periph";
		};

		/* peripheral clock for system timer */
		axi_clk: axi_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&armpll>;
			clock-div = <2>;
			clock-mult = <1>;
		};

		/* APB bus clock */
		apb_clk: apb_clk {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clocks = <&armpll>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	/* ARM bus */
	axi@80000000 {
		compatible = "simple-bus";
		ranges = <0 0x80000000 0x784000>;
		#address-cells = <1>;
		#size-cells = <1>;

		L2: cache-controller@1d000 {
			compatible = "arm,pl310-cache";
			reg = <0x1d000 0x1000>;
			cache-unified;
			cache-level = <2>;
			cache-size = <524288>;
			cache-sets = <1024>;
			cache-line-size = <32>;
			interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
		};

		scu: scu@1e000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0x1e000 0x100>;
		};

		gic: interrupt-controller@1f000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x1f000 0x1000
				0x1e100 0x100>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
		};

		global_timer: timer@1e200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x1e200 0x20>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
			clocks = <&axi_clk>;
		};

		local_timer: local-timer@1e600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x1e600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_EDGE_RISING)>;
			clocks = <&axi_clk>;
		};

		twd_watchdog: watchdog@1e620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x1e620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
		};

		armpll: armpll@20000 {
			#clock-cells = <0>;
			compatible = "brcm,bcm63138-armpll";
			clocks = <&periph_clk>;
			reg = <0x20000 0xf00>;
		};
	};

	/* Legacy UBUS base */
	bus@fffe8000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0xfffe8000 0x8000>;

		timer0: timer@80 {
			compatible = "brcm,bcmbca-periph-timer";
			reg = <0x80 0x28>;
			clocks = <&periph_clk>;
		};

		uart0: serial@600 {
			compatible = "brcm,bcm6345-uart";
			reg = <0x600 0x20>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
			clock-names = "refclk";
			status = "disabled";
		};
	};
};