blob: 5918e644d16804a3fde2c9ef5b22817e4f808322 [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8541cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
wdenk03f5c552004-10-10 21:21:55 +000029#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050036#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000037#define CONFIG_MPC8541 1 /* MPC8541 specific */
38#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xfff80000
41
wdenk03f5c552004-10-10 21:21:55 +000042#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050043#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000045#define CONFIG_ENV_OVERWRITE
Jon Loeligerd9b94f22005-07-25 14:05:07 -050046
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060047#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk03f5c552004-10-10 21:21:55 +000048
Jon Loeliger25eedb22008-03-19 15:02:07 -050049#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050050
wdenk03f5c552004-10-10 21:21:55 +000051#ifndef __ASSEMBLY__
52extern unsigned long get_clock_freq(void);
53#endif
54#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
55
56/*
57 * These can be toggled for performance analysis, otherwise use default.
58 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020059#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000060#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000061
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
63#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000064
wdenk03f5c552004-10-10 21:21:55 +000065/*
66 * Base addresses -- Note these are effective addresses where the
67 * actual resources get mapped (not physical addresses)
68 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
70#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
71#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
72#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk03f5c552004-10-10 21:21:55 +000073
Jon Loeligeraa11d852008-03-17 15:48:18 -050074/* DDR Setup */
75#define CONFIG_FSL_DDR1
76#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
77#define CONFIG_DDR_SPD
78#undef CONFIG_FSL_DDR_INTERACTIVE
79
80#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
83#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000084
Jon Loeligeraa11d852008-03-17 15:48:18 -050085#define CONFIG_NUM_DDR_CONTROLLERS 1
86#define CONFIG_DIMM_SLOTS_PER_CTLR 1
87#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
88
89/* I2C addresses of SPD EEPROMs */
90#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk03f5c552004-10-10 21:21:55 +000091
92/*
93 * Make sure required options are set
94 */
95#ifndef CONFIG_SPD_EEPROM
96#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
97#endif
98
Jon Loeliger7202d432005-07-25 11:13:26 -050099#undef CONFIG_CLOCKS_IN_MHZ
100
wdenk03f5c552004-10-10 21:21:55 +0000101/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500102 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +0000103 */
Jon Loeliger7202d432005-07-25 11:13:26 -0500104
105/*
106 * FLASH on the Local Bus
107 * Two banks, 8M each, using the CFI driver.
108 * Boot from BR0/OR0 bank at 0xff00_0000
109 * Alternate BR1/OR1 bank at 0xff80_0000
110 *
111 * BR0, BR1:
112 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
113 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
114 * Port Size = 16 bits = BRx[19:20] = 10
115 * Use GPCM = BRx[24:26] = 000
116 * Valid = BRx[31] = 1
117 *
118 * 0 4 8 12 16 20 24 28
119 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
120 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
121 *
122 * OR0, OR1:
123 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
124 * Reserved ORx[17:18] = 11, confusion here?
125 * CSNT = ORx[20] = 1
126 * ACS = half cycle delay = ORx[21:22] = 11
127 * SCY = 6 = ORx[24:27] = 0110
128 * TRLX = use relaxed timing = ORx[29] = 1
129 * EAD = use external address latch delay = OR[31] = 1
130 *
131 * 0 4 8 12 16 20 24 28
132 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
133 */
134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BR0_PRELIM 0xff801001
138#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_OR0_PRELIM 0xff806e65
141#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
144#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
145#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
146#undef CONFIG_SYS_FLASH_CHECKSUM
147#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
148#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000149
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200150#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000151
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200152#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_CFI
154#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000155
wdenk03f5c552004-10-10 21:21:55 +0000156
157/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500158 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
161#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000162
163/*
164 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000166 *
167 * For BR2, need:
168 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
169 * port-size = 32-bits = BR2[19:20] = 11
170 * no parity checking = BR2[21:22] = 00
171 * SDRAM for MSEL = BR2[24:26] = 011
172 * Valid = BR[31] = 1
173 *
174 * 0 4 8 12 16 20 24 28
175 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
176 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000178 * FIXME: the top 17 bits of BR2.
179 */
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000182
183/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000185 *
186 * For OR2, need:
187 * 64MB mask for AM, OR2[0:7] = 1111 1100
188 * XAM, OR2[17:18] = 11
189 * 9 columns OR2[19-21] = 010
190 * 13 rows OR2[23-25] = 100
191 * EAD set for extra time OR[31] = 1
192 *
193 * 0 4 8 12 16 20 24 28
194 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
195 */
196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
200#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
201#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
202#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000203
204/*
wdenk03f5c552004-10-10 21:21:55 +0000205 * Common settings for all Local Bus SDRAM commands.
206 * At run time, either BSMA1516 (for CPU 1.1)
207 * or BSMA1617 (for CPU 1.0) (old)
208 * is OR'ed in too.
209 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500210#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
211 | LSDMR_PRETOACT7 \
212 | LSDMR_ACTTORW7 \
213 | LSDMR_BL8 \
214 | LSDMR_WRC4 \
215 | LSDMR_CL3 \
216 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000217 )
218
219/*
220 * The CADMUS registers are connected to CS3 on CDS.
221 * The new memory map places CADMUS at 0xf8000000.
222 *
223 * For BR3, need:
224 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
225 * port-size = 8-bits = BR[19:20] = 01
226 * no parity checking = BR[21:22] = 00
227 * GPMC for MSEL = BR[24:26] = 000
228 * Valid = BR[31] = 1
229 *
230 * 0 4 8 12 16 20 24 28
231 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
232 *
233 * For OR3, need:
234 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
235 * disable buffer ctrl OR[19] = 0
236 * CSNT OR[20] = 1
237 * ACS OR[21:22] = 11
238 * XACS OR[23] = 1
239 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
240 * SETA OR[28] = 0
241 * TRLX OR[29] = 1
242 * EHTR OR[30] = 1
243 * EAD extra time OR[31] = 1
244 *
245 * 0 4 8 12 16 20 24 28
246 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
247 */
248
Jon Loeliger25eedb22008-03-19 15:02:07 -0500249#define CONFIG_FSL_CADMUS
250
wdenk03f5c552004-10-10 21:21:55 +0000251#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_BR3_PRELIM 0xf8000801
253#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_INIT_RAM_LOCK 1
256#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200257#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000258
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200259#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
263#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000264
265/* Serial Port */
266#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_NS16550
268#define CONFIG_SYS_NS16550_SERIAL
269#define CONFIG_SYS_NS16550_REG_SIZE 1
270#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000273 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
276#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000277
278/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_HUSH_PARSER
280#ifdef CONFIG_SYS_HUSH_PARSER
281#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk03f5c552004-10-10 21:21:55 +0000282#endif
283
Matthew McClintock0e163872006-06-28 10:43:36 -0500284/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600285#define CONFIG_OF_LIBFDT 1
286#define CONFIG_OF_BOARD_SETUP 1
287#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500288
Jon Loeliger20476722006-10-20 15:50:15 -0500289/*
290 * I2C
291 */
292#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
293#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk03f5c552004-10-10 21:21:55 +0000294#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
296#define CONFIG_SYS_I2C_SLAVE 0x7F
297#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
298#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk03f5c552004-10-10 21:21:55 +0000299
Timur Tabie8d18542008-07-18 16:52:23 +0200300/* EEPROM */
301#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_I2C_EEPROM_CCID
303#define CONFIG_SYS_ID_EEPROM
304#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
305#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200306
wdenk03f5c552004-10-10 21:21:55 +0000307/*
308 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300309 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk03f5c552004-10-10 21:21:55 +0000310 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600311#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600312#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600313#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600315#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600316#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
318#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000319
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600320#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600321#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600322#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600324#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600325#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
327#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000328
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700329#ifdef CONFIG_LEGACY
330#define BRIDGE_ID 17
331#define VIA_ID 2
332#else
333#define BRIDGE_ID 28
334#define VIA_ID 4
335#endif
wdenk03f5c552004-10-10 21:21:55 +0000336
337#if defined(CONFIG_PCI)
338
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500339#define CONFIG_MPC85XX_PCI2
wdenk03f5c552004-10-10 21:21:55 +0000340#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200341#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk03f5c552004-10-10 21:21:55 +0000342
343#undef CONFIG_EEPRO100
344#undef CONFIG_TULIP
345
wdenk03f5c552004-10-10 21:21:55 +0000346#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000348
349#endif /* CONFIG_PCI */
350
351
352#if defined(CONFIG_TSEC_ENET)
353
354#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200355#define CONFIG_NET_MULTI 1
wdenk03f5c552004-10-10 21:21:55 +0000356#endif
357
358#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500359#define CONFIG_TSEC1 1
360#define CONFIG_TSEC1_NAME "TSEC0"
361#define CONFIG_TSEC2 1
362#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000363#define TSEC1_PHY_ADDR 0
364#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000365#define TSEC1_PHYIDX 0
366#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500367#define TSEC1_FLAGS TSEC_GIGABIT
368#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500369
370/* Options are: TSEC[0-1] */
371#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000372
373#endif /* CONFIG_TSEC_ENET */
374
wdenk03f5c552004-10-10 21:21:55 +0000375/*
376 * Environment
377 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200378#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200380#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
381#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000382
383#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000385
Jon Loeliger2835e512007-06-13 13:22:08 -0500386/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500387 * BOOTP options
388 */
389#define CONFIG_BOOTP_BOOTFILESIZE
390#define CONFIG_BOOTP_BOOTPATH
391#define CONFIG_BOOTP_GATEWAY
392#define CONFIG_BOOTP_HOSTNAME
393
394
395/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500396 * Command line configuration.
397 */
398#include <config_cmd_default.h>
399
400#define CONFIG_CMD_PING
401#define CONFIG_CMD_I2C
402#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600403#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500404#define CONFIG_CMD_IRQ
405#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500406#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500407
wdenk03f5c552004-10-10 21:21:55 +0000408#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500409 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000410#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500411
wdenk03f5c552004-10-10 21:21:55 +0000412
413#undef CONFIG_WATCHDOG /* watchdog disabled */
414
415/*
416 * Miscellaneous configurable options
417 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500419#define CONFIG_CMDLINE_EDITING /* Command-line editing */
420#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
422#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500423#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000425#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000427#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
429#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
430#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
431#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk03f5c552004-10-10 21:21:55 +0000432
433/*
434 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500435 * have to be in the first 64 MB of memory, since this is
wdenk03f5c552004-10-10 21:21:55 +0000436 * the maximum mapped by the Linux kernel during initialization.
437 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500438#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
439#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk03f5c552004-10-10 21:21:55 +0000440
Jon Loeliger2835e512007-06-13 13:22:08 -0500441#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000442#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
443#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
444#endif
445
wdenk03f5c552004-10-10 21:21:55 +0000446/*
447 * Environment Configuration
448 */
449
450/* The mac addresses for all ethernet interface */
451#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500452#define CONFIG_HAS_ETH0
wdenk03f5c552004-10-10 21:21:55 +0000453#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000454#define CONFIG_HAS_ETH1
wdenk03f5c552004-10-10 21:21:55 +0000455#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000456#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000457#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
458#endif
459
460#define CONFIG_IPADDR 192.168.1.253
461
462#define CONFIG_HOSTNAME unknown
463#define CONFIG_ROOTPATH /nfsroot
464#define CONFIG_BOOTFILE your.uImage
465
466#define CONFIG_SERVERIP 192.168.1.1
467#define CONFIG_GATEWAYIP 192.168.1.1
468#define CONFIG_NETMASK 255.255.255.0
469
470#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
471
472#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
473#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
474
475#define CONFIG_BAUDRATE 115200
476
477#define CONFIG_EXTRA_ENV_SETTINGS \
478 "netdev=eth0\0" \
479 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500480 "ramdiskaddr=600000\0" \
481 "ramdiskfile=your.ramdisk.u-boot\0" \
482 "fdtaddr=400000\0" \
483 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000484
485#define CONFIG_NFSBOOTCOMMAND \
486 "setenv bootargs root=/dev/nfs rw " \
487 "nfsroot=$serverip:$rootpath " \
488 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
489 "console=$consoledev,$baudrate $othbootargs;" \
490 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500491 "tftp $fdtaddr $fdtfile;" \
492 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000493
494#define CONFIG_RAMBOOTCOMMAND \
495 "setenv bootargs root=/dev/ram rw " \
496 "console=$consoledev,$baudrate $othbootargs;" \
497 "tftp $ramdiskaddr $ramdiskfile;" \
498 "tftp $loadaddr $bootfile;" \
499 "bootm $loadaddr $ramdiskaddr"
500
501#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
502
wdenk03f5c552004-10-10 21:21:55 +0000503#endif /* __CONFIG_H */