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wdenk2e5983d2003-07-15 20:04:06 +00001/*
2 * (C) Copyright 2003
3 * Texas Instruments.
4 * Kshitij Gupta <kshitij@ti.com>
5 * Configuation settings for the TI OMAP Innovator board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
34#define CONFIG_OMAP 1 /* in a TI OMAP core */
35#define CONFIG_OMAP1510 1 /* which is in a 1510 (helen) */
36#define CONFIG_INNOVATOROMAP1510 1 /* a Innovator Board */
37
38/* input clock of PLL */
39#define CONFIG_SYS_CLK_FREQ 12000000 /* the OMAP1510 Innovator has 12MHz input clock */
40
41#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
42
43#define CONFIG_MISC_INIT_R
44
45#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
46#define CONFIG_SETUP_MEMORY_TAGS 1
wdenk5779d8d2003-12-06 23:55:10 +000047#define CONFIG_INITRD_TAG 1
wdenk2e5983d2003-07-15 20:04:06 +000048
49/*
50 * Size of malloc() pool
51 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk2e5983d2003-07-15 20:04:06 +000053
54/*
55 * Hardware drivers
56 */
57/*
58#define CONFIG_DRIVER_SMC9196
59#define CONFIG_SMC9196_BASE 0x08000300
60#define CONFIG_SMC9196_EXT_PHY
61*/
Nishanth Menonac6b3622009-10-16 00:06:37 -050062#define CONFIG_NET_MULTI
63#define CONFIG_LAN91C96
wdenk2e5983d2003-07-15 20:04:06 +000064#define CONFIG_LAN91C96_BASE 0x08000300
65#define CONFIG_LAN91C96_EXT_PHY
66
67/*
68 * NS16550 Configuration
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_NS16550
71#define CONFIG_SYS_NS16550_SERIAL
72#define CONFIG_SYS_NS16550_REG_SIZE (-4)
73#define CONFIG_SYS_NS16550_CLK (CONFIG_SYS_CLK_FREQ) /* can be 12M/32Khz or 48Mhz */
74#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */
wdenk2e5983d2003-07-15 20:04:06 +000075
76/*
77 * select serial console configuration
78 */
79#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1510 Innovator */
80
81/* allow to overwrite serial and ethaddr */
82#define CONFIG_ENV_OVERWRITE
83
84#define CONFIG_ENV_OVERWRITE
85#define CONFIG_CONS_INDEX 1
86#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk2e5983d2003-07-15 20:04:06 +000088
Jon Loeligera5cb2302007-07-04 22:33:13 -050089
90/*
91 * Command line configuration.
92 */
93#include <config_cmd_default.h>
94
95#define CONFIG_CMD_DHCP
96
97
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050098/*
99 * BOOTP options
100 */
101#define CONFIG_BOOTP_SUBNETMASK
102#define CONFIG_BOOTP_GATEWAY
103#define CONFIG_BOOTP_HOSTNAME
104#define CONFIG_BOOTP_BOOTPATH
105
wdenk2e5983d2003-07-15 20:04:06 +0000106
wdenk2e5983d2003-07-15 20:04:06 +0000107#include <configs/omap1510.h>
108
109#define CONFIG_BOOTDELAY 3
wdenk5779d8d2003-12-06 23:55:10 +0000110#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=bootp"
111#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
wdenk2e5983d2003-07-15 20:04:06 +0000113
Jon Loeligera5cb2302007-07-04 22:33:13 -0500114#if defined(CONFIG_CMD_KGDB)
wdenk2e5983d2003-07-15 20:04:06 +0000115#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
116/* what's this ? it's not used anywhere */
117#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
118#endif
119
120/*
121 * Miscellaneous configurable options
122 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_LONGHELP /* undef to save memory */
124#define CONFIG_SYS_PROMPT "OMAP1510 Innovator # " /* Monitor Command Prompt */
125#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
126#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
127#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
128#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk2e5983d2003-07-15 20:04:06 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
131#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenk2e5983d2003-07-15 20:04:06 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenk2e5983d2003-07-15 20:04:06 +0000134
Ladislav Michl3791a112009-04-22 01:12:04 +0200135/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
wdenk2e5983d2003-07-15 20:04:06 +0000136 * This time is further subdivided by a local divisor.
137 */
Ladislav Michl81472d82009-03-30 18:58:41 +0200138#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE /* use timer 1 */
Ladislav Michl3791a112009-04-22 01:12:04 +0200139#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
140#define CONFIG_SYS_HZ 1000
wdenk2e5983d2003-07-15 20:04:06 +0000141
142/*-----------------------------------------------------------------------
143 * Stack sizes
144 *
145 * The stack sizes are set up in start.S using the settings below
146 */
147#define CONFIG_STACKSIZE (128*1024) /* regular stack */
148#ifdef CONFIG_USE_IRQ
149#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
150#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
151#endif
152
153/*-----------------------------------------------------------------------
154 * Physical Memory Map
155 */
156#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
157#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
158#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
159
160#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk2e5983d2003-07-15 20:04:06 +0000163
Aneesh V56ccd362011-06-09 08:54:51 -0400164#define PHYS_SRAM 0x20000000
165
wdenk2e5983d2003-07-15 20:04:06 +0000166/*-----------------------------------------------------------------------
167 * FLASH and environment organization
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
wdenk2e5983d2003-07-15 20:04:06 +0000170#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
wdenk656658d2004-10-10 22:16:06 +0000171#define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
173#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE)
174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
175#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */
176#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE }
wdenk656658d2004-10-10 22:16:06 +0000177
178/*-----------------------------------------------------------------------
179 * FLASH driver setup
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200182#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
184#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */
wdenk2e5983d2003-07-15 20:04:06 +0000185
186/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
188#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk2e5983d2003-07-15 20:04:06 +0000189
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200190#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200191#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
192#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
wdenk2e5983d2003-07-15 20:04:06 +0000194
Aneesh V56ccd362011-06-09 08:54:51 -0400195#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
196#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
197
wdenk2e5983d2003-07-15 20:04:06 +0000198#endif /* __CONFIG_H */