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Wolfgang Denk70a20472005-09-25 15:59:01 +02001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Copied from lubbock.h
10 *
11 * (C) Copyright 2004
12 * BEC Systems <http://bec-systems.com>
13 * Cliff Brake <cliff.brake@gmail.com>
14 * Configuation settings for the Accelent/Vibren PXA255 IDP
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38#include <asm/arch/pxa-regs.h>
39
40/*
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020041 * If we are developing, we might want to start U-Boot from RAM
Wolfgang Denk70a20472005-09-25 15:59:01 +020042 * so we MUST NOT initialize critical regs like mem-timing ...
43 */
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020044#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
Marek Vasut65bd6a92010-10-20 21:20:07 +020045#define CONFIG_SYS_TEXT_BASE 0x0
Wolfgang Denk70a20472005-09-25 15:59:01 +020046
47/*
48 * define the following to enable debug blinks. A debug blink function
49 * must be defined in memsetup.S
50 */
51#undef DEBUG_BLINK_ENABLE
52#undef DEBUG_BLINKC_ENABLE
53
54/*
55 * High Level Configuration Options
56 * (easy to change)
57 */
58#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
59
60#undef CONFIG_LCD
61#ifdef CONFIG_LCD
62#define CONFIG_SHARP_LM8V31
63#endif
64
65#define CONFIG_MMC 1
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020066#define CONFIG_DOS_PARTITION 1
Wolfgang Denk70a20472005-09-25 15:59:01 +020067#define BOARD_LATE_INIT 1
68
69#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
70
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020071/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000072#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020073
Wolfgang Denk70a20472005-09-25 15:59:01 +020074/*
75 * Size of malloc() pool
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Wolfgang Denk70a20472005-09-25 15:59:01 +020078
79/*
80 * PXA250 IDP memory map information
81 */
82
83#define IDP_CS5_ETH_OFFSET 0x03400000
84
85
86/*
87 * Hardware drivers
88 */
Ben Warren7194ab82009-10-04 22:37:03 -070089#define CONFIG_NET_MULTI
90#define CONFIG_SMC91111
Wolfgang Denk70a20472005-09-25 15:59:01 +020091#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
92#define CONFIG_SMC_USE_32_BIT 1
93/* #define CONFIG_SMC_USE_IOFUNCS */
94
95/* the following has to be set high -- suspect something is wrong with
96 * with the tftp timeout routines. FIXME!!!
97 */
98#define CONFIG_NET_RETRY_COUNT 100
99
100/*
101 * select serial console configuration
102 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +0200103#define CONFIG_PXA_SERIAL
Wolfgang Denk70a20472005-09-25 15:59:01 +0200104#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
105
106/* allow to overwrite serial and ethaddr */
107#define CONFIG_ENV_OVERWRITE
108
109#define CONFIG_BAUDRATE 115200
110
Wolfgang Denk70a20472005-09-25 15:59:01 +0200111
Jon Loeliger26a34562007-07-04 22:33:17 -0500112/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500113 * BOOTP options
114 */
115#define CONFIG_BOOTP_BOOTFILESIZE
116#define CONFIG_BOOTP_BOOTPATH
117#define CONFIG_BOOTP_GATEWAY
118#define CONFIG_BOOTP_HOSTNAME
119
120
121/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500122 * Command line configuration.
123 */
124#include <config_cmd_default.h>
125
Jon Loeliger26a34562007-07-04 22:33:17 -0500126#define CONFIG_CMD_FAT
127#define CONFIG_CMD_DHCP
128
Wolfgang Denk70a20472005-09-25 15:59:01 +0200129#define CONFIG_BOOTDELAY 3
130#define CONFIG_BOOTCOMMAND "bootm 40000"
131#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
Wolfgang Denk25dbe982008-07-13 23:07:35 +0200132
133#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
134#define CONFIG_SETUP_MEMORY_TAGS 1
135/* #define CONFIG_INITRD_TAG 1 */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200136
137/*
138 * Current memory map for Vibren supplied Linux images:
139 *
140 * Flash:
141 * 0 - 0x3ffff (size = 0x40000): bootloader
142 * 0x40000 - 0x13ffff (size = 0x100000): kernel
143 * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
144 *
145 * RAM:
146 * 0xa0008000 - kernel is loaded
147 * 0xa3000000 - Uboot runs (48MB into RAM)
148 *
149 */
150
151#define CONFIG_EXTRA_ENV_SETTINGS \
152 "prog_boot_mmc=" \
153 "mw.b 0xa0000000 0xff 0x40000; " \
154 "if mmcinit && " \
155 "fatload mmc 0 0xa0000000 u-boot.bin; " \
156 "then " \
157 "protect off 0x0 0x3ffff; " \
158 "erase 0x0 0x3ffff; " \
159 "cp.b 0xa0000000 0x0 0x40000; " \
160 "reset;" \
161 "fi\0" \
162 "prog_uzImage_mmc=" \
163 "mw.b 0xa0000000 0xff 0x100000; " \
164 "if mmcinit && " \
165 "fatload mmc 0 0xa0000000 uzImage; " \
166 "then " \
167 "protect off 0x40000 0xfffff; " \
168 "erase 0x40000 0xfffff; " \
169 "cp.b 0xa0000000 0x40000 0x100000; " \
170 "fi\0" \
171 "prog_jffs_mmc=" \
172 "mw.b 0xa0000000 0xff 0x1e00000; " \
173 "if mmcinit && " \
174 "fatload mmc 0 0xa0000000 root.jffs; " \
175 "then " \
176 "protect off 0x140000 0x1f3ffff; " \
177 "erase 0x140000 0x1f3ffff; " \
178 "cp.b 0xa0000000 0x140000 0x1e00000; " \
179 "fi\0" \
180 "boot_mmc=" \
181 "if mmcinit && " \
182 "fatload mmc 0 0xa1000000 uzImage && " \
183 "then " \
184 "bootm 0xa1000000; " \
185 "fi\0" \
186 "prog_boot_net=" \
187 "mw.b 0xa0000000 0xff 0x100000; " \
188 "if bootp 0xa0000000 u-boot.bin; " \
189 "then " \
190 "protect off 0x0 0x3ffff; " \
191 "erase 0x0 0x3ffff; " \
192 "cp.b 0xa0000000 0x0 0x40000; " \
193 "reset; " \
194 "fi\0" \
195 "prog_uzImage_net=" \
196 "mw.b 0xa0000000 0xff 0x100000; " \
197 "if bootp 0xa0000000 uzImage; " \
198 "then " \
199 "protect off 0x40000 0xfffff; " \
200 "erase 0x40000 0xfffff; " \
201 "cp.b 0xa0000000 0x40000 0x100000; " \
202 "fi\0" \
203 "prog_jffs_net=" \
204 "mw.b 0xa0000000 0xff 0x1e00000; " \
205 "if bootp 0xa0000000 root.jffs; " \
206 "then " \
207 "protect off 0x140000 0x1f3ffff; " \
208 "erase 0x140000 0x1f3ffff; " \
209 "cp.b 0xa0000000 0x140000 0x1e00000; " \
210 "fi\0"
211
212
213/* "erase_env=" */
214/* "protect off" */
215
216
Jon Loeliger26a34562007-07-04 22:33:17 -0500217#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200218#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
219#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
220#endif
221
222/*
223 * Miscellaneous configurable options
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_HUSH_PARSER 1
226#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wolfgang Denk70a20472005-09-25 15:59:01 +0200227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_LONGHELP /* undef to save memory */
229#ifdef CONFIG_SYS_HUSH_PARSER
230#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200231#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200233#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
235#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
236#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
237#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
238#define CONFIG_SYS_DEVICE_NULLDEV 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
241#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200244
Micha Kalfon94a33122009-02-11 19:50:11 +0200245#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200247
248#define RTC 1 /* enable 32KHz osc */
249
250 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denk70a20472005-09-25 15:59:01 +0200252
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100253#ifdef CONFIG_MMC
254#define CONFIG_PXA_MMC
255#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100257#endif
Wolfgang Denk70a20472005-09-25 15:59:01 +0200258
259/*
260 * Stack sizes
261 *
262 * The stack sizes are set up in start.S using the settings below
263 */
264#define CONFIG_STACKSIZE (128*1024) /* regular stack */
265#ifdef CONFIG_USE_IRQ
266#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
267#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
268#endif
269
270/*
271 * Physical Memory Map
272 */
Marek Vasut65bd6a92010-10-20 21:20:07 +0200273#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200274#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
275#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
276#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
277#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
278#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
279#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
280#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
281#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
282
283#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
284#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
285#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
286#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
287#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_DRAM_BASE 0xa0000000
290#define CONFIG_SYS_DRAM_SIZE 0x04000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200293
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200294#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200295#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200296
Wolfgang Denk70a20472005-09-25 15:59:01 +0200297/*
298 * GPIO settings
299 */
300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
302#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
303#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
304#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
305#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
306#define CONFIG_SYS_GAFR2_U_VAL 0x2
307#define CONFIG_SYS_GPCR0_VAL 0x1800400
308#define CONFIG_SYS_GPCR1_VAL 0x0
309#define CONFIG_SYS_GPCR2_VAL 0x0
310#define CONFIG_SYS_GPDR0_VAL 0xc1818440
311#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
312#define CONFIG_SYS_GPDR2_VAL 0x1ffff
313#define CONFIG_SYS_GPSR0_VAL 0x8000
314#define CONFIG_SYS_GPSR1_VAL 0x3f0002
315#define CONFIG_SYS_GPSR2_VAL 0x1c000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_PSSR_VAL 0x20
Wolfgang Denk70a20472005-09-25 15:59:01 +0200318
Marek Vasut65bd6a92010-10-20 21:20:07 +0200319#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
320#define CONFIG_SYS_CKEN 0x0
321
Wolfgang Denk70a20472005-09-25 15:59:01 +0200322/*
323 * Memory settings
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
326#define CONFIG_SYS_MSC1_VAL 0x43AC494C
327#define CONFIG_SYS_MSC2_VAL 0x39D449D4
328#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
329#define CONFIG_SYS_MDREFR_VAL 0x0085C017
330#define CONFIG_SYS_MDMRS_VAL 0x00220022
Marek Vasut65bd6a92010-10-20 21:20:07 +0200331#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
332#define CONFIG_SYS_SXCNFG_VAL 0x00000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200333
334/*
335 * PCMCIA and CF Interfaces
336 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_MECR_VAL 0x00000003
338#define CONFIG_SYS_MCMEM0_VAL 0x00014405
339#define CONFIG_SYS_MCMEM1_VAL 0x00014405
340#define CONFIG_SYS_MCATT0_VAL 0x00014405
341#define CONFIG_SYS_MCATT1_VAL 0x00014405
342#define CONFIG_SYS_MCIO0_VAL 0x00014405
343#define CONFIG_SYS_MCIO1_VAL 0x00014405
Wolfgang Denk70a20472005-09-25 15:59:01 +0200344
345/*
346 * FLASH and environment organization
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200349#define CONFIG_FLASH_CFI_DRIVER 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_MONITOR_BASE 0
352#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Wolfgang Denk70a20472005-09-25 15:59:01 +0200353
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
355#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200358
359/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
361#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200362
363/* put cfg at end of flash for now */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200364#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200365 /* Addr of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200366#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
367#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
368#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200369
370#endif /* __CONFIG_H */