blob: c5d581589aa1dba0d8921e739719d2b9c99beefe [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00007 */
8
wdenk0ac6f8b2004-07-09 23:27:13 +00009/*
10 * mpc8540ads board configuration file
11 *
12 * Please refer to doc/README.mpc85xx for more info.
13 *
14 * Make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050015 * search for CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021/*
22 * default CCARBAR is at 0xff700000
23 * assume U-Boot is less than 0.5MB
24 */
25#define CONFIG_SYS_TEXT_BASE 0xfff80000
26
Jon Loeliger288693a2005-07-25 12:14:54 -050027#ifndef CONFIG_HAS_FEC
28#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
29#endif
30
Gabor Juhos842033e2013-05-30 07:06:12 +000031#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050032#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020033#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000034#define CONFIG_ENV_OVERWRITE
wdenk42d1f032003-10-15 23:53:47 +000035
wdenk0ac6f8b2004-07-09 23:27:13 +000036/*
37 * sysclk for MPC85xx
38 *
39 * Two valid values are:
40 * 33000000
41 * 66000000
42 *
43 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000044 * is likely the desired value here, so that is now the default.
45 * The board, however, can run at 66MHz. In any event, this value
46 * must match the settings of some switches. Details can be found
47 * in the README.mpc85xxads.
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050048 *
49 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
50 * 33MHz to accommodate, based on a PCI pin.
51 * Note that PCI-X won't work at 33MHz.
wdenk0ac6f8b2004-07-09 23:27:13 +000052 */
53
wdenk9aea9532004-08-01 23:02:45 +000054#ifndef CONFIG_SYS_CLK_FREQ
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050055#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000056#endif
57
wdenk0ac6f8b2004-07-09 23:27:13 +000058/*
59 * These can be toggled for performance analysis, otherwise use default.
60 */
61#define CONFIG_L2_CACHE /* toggle L2 cache */
62#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000063
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
65#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000066
Timur Tabie46fedf2011-08-04 18:03:41 -050067#define CONFIG_SYS_CCSRBAR 0xe0000000
68#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000069
Kumar Gala9617c8d2008-06-06 13:12:18 -050070/* DDR Setup */
Kumar Gala9617c8d2008-06-06 13:12:18 -050071#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
72#define CONFIG_DDR_SPD
73#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000074
Kumar Gala9617c8d2008-06-06 13:12:18 -050075#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
76
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
78#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +000079
Kumar Gala9617c8d2008-06-06 13:12:18 -050080#define CONFIG_DIMM_SLOTS_PER_CTLR 1
81#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +000082
Kumar Gala9617c8d2008-06-06 13:12:18 -050083/* I2C addresses of SPD EEPROMs */
84#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +000085
Kumar Gala9617c8d2008-06-06 13:12:18 -050086/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
88#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
89#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
90#define CONFIG_SYS_DDR_TIMING_1 0x37344321
91#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
92#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
93#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
94#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +000095
wdenk0ac6f8b2004-07-09 23:27:13 +000096/*
97 * SDRAM on the Local Bus
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
100#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
103#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
106#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
107#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
108#undef CONFIG_SYS_FLASH_CHECKSUM
109#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
110#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000111
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200112#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
115#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000116#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000118#endif
119
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200120#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_FLASH_CFI
122#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk42d1f032003-10-15 23:53:47 +0000123
wdenk42d1f032003-10-15 23:53:47 +0000124#undef CONFIG_CLOCKS_IN_MHZ
125
wdenk0ac6f8b2004-07-09 23:27:13 +0000126/*
127 * Local Bus Definitions
128 */
129
130/*
131 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000133 *
134 * For BR2, need:
135 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
136 * port-size = 32-bits = BR2[19:20] = 11
137 * no parity checking = BR2[21:22] = 00
138 * SDRAM for MSEL = BR2[24:26] = 011
139 * Valid = BR[31] = 1
140 *
141 * 0 4 8 12 16 20 24 28
142 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
143 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000145 * FIXME: the top 17 bits of BR2.
146 */
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000149
150/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000152 *
153 * For OR2, need:
154 * 64MB mask for AM, OR2[0:7] = 1111 1100
155 * XAM, OR2[17:18] = 11
156 * 9 columns OR2[19-21] = 010
157 * 13 rows OR2[23-25] = 100
158 * EAD set for extra time OR[31] = 1
159 *
160 * 0 4 8 12 16 20 24 28
161 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
162 */
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
167#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
168#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
169#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000170
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500171#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
172 | LSDMR_RFCR5 \
173 | LSDMR_PRETOACT3 \
174 | LSDMR_ACTTORW3 \
175 | LSDMR_BL8 \
176 | LSDMR_WRC2 \
177 | LSDMR_CL3 \
178 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000179 )
180
181/*
182 * SDRAM Controller configuration sequence.
183 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500184#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
185#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
186#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
187#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
188#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000189
wdenk9aea9532004-08-01 23:02:45 +0000190/*
191 * 32KB, 8-bit wide for ADS config reg
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_BR4_PRELIM 0xf8000801
194#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
195#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_INIT_RAM_LOCK 1
198#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200199#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000200
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200201#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
205#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000206
207/* Serial Port */
208#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_NS16550_SERIAL
210#define CONFIG_SYS_NS16550_REG_SIZE 1
211#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk42d1f032003-10-15 23:53:47 +0000212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
217#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk42d1f032003-10-15 23:53:47 +0000218
Jon Loeliger20476722006-10-20 15:50:15 -0500219/*
220 * I2C
221 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200222#define CONFIG_SYS_I2C
223#define CONFIG_SYS_I2C_FSL
224#define CONFIG_SYS_FSL_I2C_SPEED 400000
225#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
226#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
227#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk42d1f032003-10-15 23:53:47 +0000228
wdenk0ac6f8b2004-07-09 23:27:13 +0000229/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600230#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600231#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600232#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000234
235/*
236 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300237 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000238 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600239#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600240#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600241#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600243#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600244#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
246#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000247
wdenk42d1f032003-10-15 23:53:47 +0000248#if defined(CONFIG_PCI)
wdenk42d1f032003-10-15 23:53:47 +0000249#undef CONFIG_EEPRO100
wdenk0ac6f8b2004-07-09 23:27:13 +0000250#undef CONFIG_TULIP
251
252#if !defined(CONFIG_PCI_PNP)
253 #define PCI_ENET0_IOADDR 0xe0000000
254 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200255 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000256#endif
257
wdenk0ac6f8b2004-07-09 23:27:13 +0000258#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000260
261#endif /* CONFIG_PCI */
262
wdenk0ac6f8b2004-07-09 23:27:13 +0000263#if defined(CONFIG_TSEC_ENET)
264
wdenk0ac6f8b2004-07-09 23:27:13 +0000265#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500266#define CONFIG_TSEC1 1
267#define CONFIG_TSEC1_NAME "TSEC0"
268#define CONFIG_TSEC2 1
269#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000270#define TSEC1_PHY_ADDR 0
271#define TSEC2_PHY_ADDR 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000272#define TSEC1_PHYIDX 0
273#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500274#define TSEC1_FLAGS TSEC_GIGABIT
275#define TSEC2_FLAGS TSEC_GIGABIT
wdenk9aea9532004-08-01 23:02:45 +0000276
Jon Loeliger288693a2005-07-25 12:14:54 -0500277#if CONFIG_HAS_FEC
wdenk9aea9532004-08-01 23:02:45 +0000278#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500279#define CONFIG_MPC85XX_FEC_NAME "FEC"
wdenk9aea9532004-08-01 23:02:45 +0000280#define FEC_PHY_ADDR 3
wdenk0ac6f8b2004-07-09 23:27:13 +0000281#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500282#define FEC_FLAGS 0
Jon Loeliger288693a2005-07-25 12:14:54 -0500283#endif
wdenk9aea9532004-08-01 23:02:45 +0000284
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500285/* Options are: TSEC[0-1], FEC */
286#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000287
288#endif /* CONFIG_TSEC_ENET */
289
wdenk0ac6f8b2004-07-09 23:27:13 +0000290/*
291 * Environment
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200294 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200296 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
297 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000298#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200299 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200301 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000302#endif
303
wdenk0ac6f8b2004-07-09 23:27:13 +0000304#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000306
Jon Loeliger2835e512007-06-13 13:22:08 -0500307/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500308 * BOOTP options
309 */
310#define CONFIG_BOOTP_BOOTFILESIZE
311#define CONFIG_BOOTP_BOOTPATH
312#define CONFIG_BOOTP_GATEWAY
313#define CONFIG_BOOTP_HOSTNAME
314
Jon Loeliger659e2f62007-07-10 09:10:49 -0500315/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500316 * Command line configuration.
317 */
Kumar Gala1c9aa762008-09-22 23:40:42 -0500318#define CONFIG_CMD_IRQ
Jon Loeliger2835e512007-06-13 13:22:08 -0500319
320#if defined(CONFIG_PCI)
321 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000322#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000323
wdenk0ac6f8b2004-07-09 23:27:13 +0000324#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000325
326/*
327 * Miscellaneous configurable options
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500330#define CONFIG_CMDLINE_EDITING /* Command-line editing */
331#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000333
Jon Loeliger2835e512007-06-13 13:22:08 -0500334#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000336#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000338#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
341#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
342#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000343
344/*
345 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500346 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000347 * the maximum mapped by the Linux kernel during initialization.
348 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500349#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
350#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000351
Jon Loeliger2835e512007-06-13 13:22:08 -0500352#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000353#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk42d1f032003-10-15 23:53:47 +0000354#endif
355
wdenk9aea9532004-08-01 23:02:45 +0000356/*
357 * Environment Configuration
358 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000359
360/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000361#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500362#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000363#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000364#define CONFIG_HAS_ETH2
wdenk42d1f032003-10-15 23:53:47 +0000365#endif
366
wdenk0ac6f8b2004-07-09 23:27:13 +0000367#define CONFIG_IPADDR 192.168.1.253
368
369#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000370#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000371#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000372
373#define CONFIG_SERVERIP 192.168.1.1
374#define CONFIG_GATEWAYIP 192.168.1.1
375#define CONFIG_NETMASK 255.255.255.0
376
377#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
378
wdenk0ac6f8b2004-07-09 23:27:13 +0000379#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
380
wdenk9aea9532004-08-01 23:02:45 +0000381#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk0ac6f8b2004-07-09 23:27:13 +0000382 "netdev=eth0\0" \
383 "consoledev=ttyS0\0" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500384 "ramdiskaddr=1000000\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500385 "ramdiskfile=your.ramdisk.u-boot\0" \
386 "fdtaddr=400000\0" \
387 "fdtfile=your.fdt.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000388
wdenk9aea9532004-08-01 23:02:45 +0000389#define CONFIG_NFSBOOTCOMMAND \
wdenk0ac6f8b2004-07-09 23:27:13 +0000390 "setenv bootargs root=/dev/nfs rw " \
391 "nfsroot=$serverip:$rootpath " \
392 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
393 "console=$consoledev,$baudrate $othbootargs;" \
394 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500395 "tftp $fdtaddr $fdtfile;" \
396 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000397
398#define CONFIG_RAMBOOTCOMMAND \
399 "setenv bootargs root=/dev/ram rw " \
400 "console=$consoledev,$baudrate $othbootargs;" \
401 "tftp $ramdiskaddr $ramdiskfile;" \
402 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500403 "tftp $fdtaddr $fdtfile;" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500404 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000405
406#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000407
408#endif /* __CONFIG_H */