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Wolfgang Denk6bdf4302005-08-15 15:55:00 +02001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
26 * U-Boot port on STx XTc 8xx board
27 * Mostly copied from Panto's NETTA2 board.
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
39#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
40
41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44
Wolfgang Denk670d9f12005-09-13 00:12:33 +020045#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020046
47#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
48
49/* Select one of few clock rates defined later in this file.
50*/
51/* #define MPC8XX_HZ 50000000 */
52#define MPC8XX_HZ 66666666
53
54#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
55
56#if 0
57#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58#else
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60#endif
61
62#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
63
64#undef CONFIG_BOOTARGS
65#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020066 "tftpboot; " \
67 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
68 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020069 "bootm"
70
71#define CONFIG_AUTOSCRIPT
72#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020074
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76
77#define CONFIG_STATUS_LED 1 /* Status LED enabled */
78#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
79
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050080/*
81 * BOOTP options
82 */
83#define CONFIG_BOOTP_SUBNETMASK
84#define CONFIG_BOOTP_GATEWAY
85#define CONFIG_BOOTP_HOSTNAME
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_BOOTFILESIZE
88#define CONFIG_BOOTP_NISDOMAIN
89
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020090
91#undef CONFIG_MAC_PARTITION
92#undef CONFIG_DOS_PARTITION
93
94#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
95
Wolfgang Denk53677ef2008-05-20 16:00:29 +020096#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020097#define FEC_ENET 1 /* eth.c needs it that way... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_DISCOVER_PHY
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020099#define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500100#define CONFIG_MII_INIT 1
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200101#undef CONFIG_RMII
102
103#define CONFIG_ETHER_ON_FEC1 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200104#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200105#undef CONFIG_FEC1_PHY_NORXERR
106
107#define CONFIG_ETHER_ON_FEC2 1
108#define CONFIG_FEC2_PHY 3
109#undef CONFIG_FEC2_PHY_NORXERR
110
111#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
112
Jon Loeligeref0df522007-07-04 22:31:07 -0500113
114/*
115 * Command line configuration.
116 */
117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_MII
121#define CONFIG_CMD_NAND
122#define CONFIG_CMD_NFS
123#define CONFIG_CMD_PING
124
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200125
126#define CONFIG_BOARD_EARLY_INIT_F 1
127#define CONFIG_MISC_INIT_R
128
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200129/*
130 * Miscellaneous configurable options
131 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LONGHELP /* undef to save memory */
133#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_HUSH_PARSER 1
136#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200137
Jon Loeligeref0df522007-07-04 22:31:07 -0500138#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200140#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200142#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
144#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
148#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200155
156/*
157 * Low Level Configuration Settings
158 * (address mappings, register initial values, etc.)
159 * You should know what you are doing if you make changes here.
160 */
161/*-----------------------------------------------------------------------
162 * Internal Memory Mapped Register
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_IMMR 0xFF000000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200165
166/*-----------------------------------------------------------------------
167 * Definitions for initial stack pointer and data area (in DPRAM)
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
170#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
171#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
172#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
173#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200174
175/*-----------------------------------------------------------------------
176 * Start addresses for the final memory configuration
177 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_SDRAM_BASE 0x00000000
181#define CONFIG_SYS_FLASH_BASE 0x40000000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200182#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200184#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200186#endif
187
188/* yes this is weird, I know :) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
190#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_RESET_ADDRESS 0x80000000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200193
194/*
195 * For booting Linux, the board info and command line data
196 * have to be in the first 8 MB of memory, since this is
197 * the maximum mapped by the Linux kernel during initialization.
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200200
201/*-----------------------------------------------------------------------
202 * FLASH organization
203 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200204#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200205#define CONFIG_ENV_SECT_SIZE 0x10000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200208#define CONFIG_ENV_OFFSET 0
209#define CONFIG_ENV_SIZE 0x4000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_OFFSET_REDUND 0
213#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200216#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
218#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
219#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_FLASH_PROTECTION
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200224
225/*-----------------------------------------------------------------------
226 * Cache Configuration
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligeref0df522007-07-04 22:31:07 -0500229#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200231#endif
232
233/*-----------------------------------------------------------------------
234 * SYPCR - System Protection Control 11-9
235 * SYPCR can only be written once after reset!
236 *-----------------------------------------------------------------------
237 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
238 */
239#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200241 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
242#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200244#endif
245
246/*-----------------------------------------------------------------------
247 * SIUMCR - SIU Module Configuration 11-6
248 *-----------------------------------------------------------------------
249 * PCMCIA config., multi-function pin tri-state
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200252
253/*-----------------------------------------------------------------------
254 * TBSCR - Time Base Status and Control 11-26
255 *-----------------------------------------------------------------------
256 * Clear Reference Interrupt Status, Timebase freezing enabled
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200259
260/*-----------------------------------------------------------------------
261 * RTCSC - Real-Time Clock Status and Control Register 11-27
262 *-----------------------------------------------------------------------
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200265
266/*-----------------------------------------------------------------------
267 * PISCR - Periodic Interrupt Status and Control 11-31
268 *-----------------------------------------------------------------------
269 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
270 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200272
273/*-----------------------------------------------------------------------
274 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
275 *-----------------------------------------------------------------------
276 * Reset PLL lock status sticky bit, timer expired status bit and timer
277 * interrupt status bit
278 *
279 */
280
281#if CONFIG_XIN == 10000000
282
283#if MPC8XX_HZ == 50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200285 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200286 PLPRCR_TEXPS)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200287#elif MPC8XX_HZ == 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200289 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200290 PLPRCR_TEXPS)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200291#else
292#error unsupported CPU freq for XIN = 10MHz
293#endif
294#else
295#error unsupported freq for XIN (must be 10MHz)
296#endif
297
298
299/*
300 *-----------------------------------------------------------------------
301 * SCCR - System Clock and reset Control Register 15-27
302 *-----------------------------------------------------------------------
303 * Set clock output, timebase and RTC source and divider,
304 * power management and some other internal clocks
305 *
306 * Note: When TBS == 0 the timebase is independent of current cpu clock.
307 */
308
309#define SCCR_MASK SCCR_EBDF11
310#if MPC8XX_HZ > 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200312 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
313 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
314 SCCR_DFALCD00 | SCCR_EBDF01)
315#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200317 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
318 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
319 SCCR_DFALCD00)
320#endif
321
322/*-----------------------------------------------------------------------
323 *
324 *-----------------------------------------------------------------------
325 *
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327/*#define CONFIG_SYS_DER 0x2002000F*/
328#define CONFIG_SYS_DER 0
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200329
330/*
331 * Init Memory Controller:
332 *
333 * BR0/1 and OR0/1 (FLASH)
334 */
335
336#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
337#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
338
339/* used to re-map FLASH both when starting from SRAM or FLASH:
340 * restrict access enough to keep SRAM working (if any)
341 * but not too much to meddle with FLASH accesses
342 */
343
344#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_REMAP_OR_AM 0x80000000
347#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200348
349/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
353#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
354#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
357#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200358
359/*
360 * BR4 and OR4 (SDRAM)
361 *
362 */
363#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
364#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
365
366/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
370#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200371
372/*
373 * Memory Periodic Timer Prescaler
374 */
375
376/*
377 * Memory Periodic Timer Prescaler
378 *
379 * The Divider for PTA (refresh timer) configuration is based on an
380 * example SDRAM configuration (64 MBit, one bank). The adjustment to
381 * the number of chip selects (NCS) and the actually needed refresh
382 * rate is done by setting MPTPR.
383 *
384 * PTA is calculated from
385 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
386 *
387 * gclk CPU clock (not bus clock!)
388 * Trefresh Refresh cycle * 4 (four word bursts used)
389 *
390 * 4096 Rows from SDRAM example configuration
391 * 1000 factor s -> ms
392 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
393 * 4 Number of refresh cycles per period
394 * 64 Refresh cycle in ms per number of rows
395 * --------------------------------------------
396 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
397 *
398 * 50 MHz => 50.000.000 / Divider = 98
399 * 66 Mhz => 66.000.000 / Divider = 129
400 * 80 Mhz => 80.000.000 / Divider = 156
401 */
402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_MAMR_PTA 234
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200404
405/*
406 * For 16 MBit, refresh rates could be 31.3 us
407 * (= 64 ms / 2K = 125 / quad bursts).
408 * For a simpler initialization, 15.6 us is used instead.
409 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
411 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200412 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
414#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200415
416/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
418#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200419
420/*
421 * MAMR settings for SDRAM
422 */
423
424/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200426 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
427 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
428
429/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200431 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
432 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
433
434/*
435 * Internal Definitions
436 *
437 * Boot Flags
438 */
439#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
440#define BOOTFLAG_WARM 0x02 /* Software reboot */
441
442#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
443
444/****************************************************************/
445
446#define NAND_SIZE 0x00010000 /* 64K */
447#define NAND_BASE 0xF1000000
448
449/****************************************************************/
450
451/* NAND */
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200452#define CONFIG_NAND_LEGACY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_NAND_BASE NAND_BASE
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200454#define CONFIG_MTD_NAND_ECC_JFFS2
455#define CONFIG_MTD_NAND_VERIFY_WRITE
456#define CONFIG_MTD_NAND_UNSAFE
457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200459#undef NAND_NO_RB
460
461#define SECTORSIZE 512
462#define ADDR_COLUMN 1
463#define ADDR_PAGE 2
464#define ADDR_COLUMN_PAGE 3
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200465#define NAND_ChipID_UNKNOWN 0x00
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200466#define NAND_MAX_FLOORS 1
467#define NAND_MAX_CHIPS 1
468
469/* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
470#define NAND_DISABLE_CE(nand) \
471 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200473 } while(0)
474
475#define NAND_ENABLE_CE(nand) \
476 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200478 } while(0)
479
480#define NAND_CTL_CLRALE(nandptr) \
481 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200483 } while(0)
484
485#define NAND_CTL_SETALE(nandptr) \
486 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200488 } while(0)
489
490#define NAND_CTL_CLRCLE(nandptr) \
491 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200493 } while(0)
494
495#define NAND_CTL_SETCLE(nandptr) \
496 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200498 } while(0)
499
500#ifndef NAND_NO_RB
501#define NAND_WAIT_READY(nand) \
502 do { \
503 int _tries = 0; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200505 if (++_tries > 100000) \
506 break; \
507 } while (0)
508#else
509#define NAND_WAIT_READY(nand) udelay(12)
510#endif
511
512#define WRITE_NAND_COMMAND(d, adr) \
513 do { \
514 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
515 } while(0)
516
517#define WRITE_NAND_ADDRESS(d, adr) \
518 do { \
519 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
520 } while(0)
521
522#define WRITE_NAND(d, adr) \
523 do { \
524 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
525 } while(0)
526
527#define READ_NAND(adr) \
528 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
529
530/*****************************************************************************/
531
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_DIRECT_FLASH_TFTP
533#define CONFIG_SYS_DIRECT_NAND_TFTP
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200534
535/*****************************************************************************/
536
537/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
538 * CxOE and CxRESET. We use the CxOE.
539 */
540#define STATUS_LED_BIT 0x00000080 /* bit 24 */
541
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200543#define STATUS_LED_STATE STATUS_LED_BLINKING
544
545#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
546#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
547
548#ifndef __ASSEMBLY__
549
550/* LEDs */
551
552/* led_id_t is unsigned int mask */
553typedef unsigned int led_id_t;
554
555#define __led_toggle(_msk) \
556 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200558 } while(0)
559
560#define __led_set(_msk, _st) \
561 do { \
562 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200564 else \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200566 } while(0)
567
568#define __led_init(msk, st) __led_set(msk, st)
569
570#endif
571
572/******************************************************************************/
573
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200574#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
575#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
576#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200577
578/******************************************************************************/
579
580/* use board specific hardware */
581#undef CONFIG_WATCHDOG /* watchdog disabled */
582#define CONFIG_HW_WATCHDOG
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200583
584/*****************************************************************************/
585
586#define CONFIG_AUTO_COMPLETE 1
587#define CONFIG_CRC32_VERIFY 1
588#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
589
Wolfgang Denk070610c2005-10-13 01:49:09 +0200590/*****************************************************************************/
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200591
Gerald Van Baren62bcdda2008-06-03 20:26:29 -0400592/* pass open firmware flattened device tree */
593#define CONFIG_OF_LIBFDT 1
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200594
Wolfgang Denk070610c2005-10-13 01:49:09 +0200595#define OF_CPU "PowerPC,MPC870@0"
596#define OF_TBCLK (MPC8XX_HZ / 16)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200597
598#endif /* __CONFIG_H */