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Dan Malek35171dc2007-01-05 09:15:34 +01001/*
2 * Copyright (C) 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
4 * Copied from STx GP3.
5 * Updates for Silicon Tx GP3 SSA. We only support 32-bit flash
6 * and DDR with SPD EEPROM configuration.
7 *
8 * Copyright 2004 Freescale Semiconductor.
9 * Copyright (C) 2002,2003, Motorola Inc.
10 * Xianghua Xiao <X.Xiao@motorola.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <ppc_asm.tmpl>
32#include <ppc_defs.h>
33#include <asm/cache.h>
34#include <asm/mmu.h>
35#include <config.h>
36#include <mpc85xx.h>
37
38
39/*
40 * TLB0 and TLB1 Entries
41 *
42 * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
43 * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
44 * these TLB entries are established.
45 *
46 * The TLB entries for DDR are dynamically setup in spd_sdram()
47 * and use TLB1 Entries 8 through 15 as needed according to the
48 * size of DDR memory.
49 *
50 * MAS0: tlbsel, esel, nv
51 * MAS1: valid, iprot, tid, ts, tsize
Kumar Gala2146cf52007-12-19 01:18:15 -060052 * MAS2: epn, x0, x1, w, i, m, g, e
Dan Malek35171dc2007-01-05 09:15:34 +010053 * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
54 */
55
56#define entry_start \
57 mflr r1 ; \
58 bl 0f ;
59
60#define entry_end \
610: mflr r0 ; \
62 mtlr r1 ; \
63 blr ;
64
65
66 .section .bootpg, "ax"
67 .globl tlb1_entry
68tlb1_entry:
69 entry_start
70
71 /*
72 * Number of TLB0 and TLB1 entries in the following table
73 */
74 .long 12
75
76#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
77 /*
78 * TLB0 4K Non-cacheable, guarded
79 * 0xff700000 4K Initial CCSRBAR mapping
80 *
81 * This ends up at a TLB0 Index==0 entry, and must not collide
82 * with other TLB0 Entries.
83 */
Kumar Gala2146cf52007-12-19 01:18:15 -060084 .long FSL_BOOKE_MAS0(0, 0, 0)
85 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
86 .long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
87 .long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +010088#else
89#error("Update the number of table entries in tlb1_entry")
90#endif
91
92 /*
93 * TLB0 16K Cacheable, non-guarded
94 * 0xd001_0000 16K Temporary Global data for initialization
95 *
96 * Use four 4K TLB0 entries. These entries must be cacheable
97 * as they provide the bootstrap memory before the memory
98 * controler and real memory have been configured.
99 *
100 * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
101 * and must not collide with other TLB0 entries.
102 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600103 .long FSL_BOOKE_MAS0(0, 0, 0)
104 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
105 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
106 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100107
Kumar Gala2146cf52007-12-19 01:18:15 -0600108 .long FSL_BOOKE_MAS0(0, 0, 0)
109 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
110 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
111 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100112
Kumar Gala2146cf52007-12-19 01:18:15 -0600113 .long FSL_BOOKE_MAS0(0, 0, 0)
114 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
115 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
116 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100117
Kumar Gala2146cf52007-12-19 01:18:15 -0600118 .long FSL_BOOKE_MAS0(0, 0, 0)
119 .long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
120 .long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
121 .long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100122
123
124 /*
125 * TLB 0: 64M Non-cacheable, guarded
126 * 0xfc000000 6M4 FLASH
127 * Out of reset this entry is only 4K.
128 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600129 .long FSL_BOOKE_MAS0(1, 0, 0)
130 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
131 .long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
132 .long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100133
134 /*
135 * TLB 1: 256M Non-cacheable, guarded
136 * 0x80000000 256M PCI1 MEM First half
137 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600138 .long FSL_BOOKE_MAS0(1, 1, 0)
139 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
Kumar Galac8c41d42008-01-16 10:04:42 -0600140 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
141 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100142
143 /*
144 * TLB 2: 256M Non-cacheable, guarded
145 * 0x90000000 256M PCI1 MEM Second half
146 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600147 .long FSL_BOOKE_MAS0(1, 2, 0)
148 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
Kumar Galac8c41d42008-01-16 10:04:42 -0600149 .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
150 .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100151
152 /*
153 * TLB 3: 256M Non-cacheable, guarded
154 * 0xa0000000 256M PCI2 MEM First half
155 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600156 .long FSL_BOOKE_MAS0(1, 3, 0)
157 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
Kumar Galac8c41d42008-01-16 10:04:42 -0600158 .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS, (MAS2_I|MAS2_G))
159 .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100160
161 /*
162 * TLB 4: 256M Non-cacheable, guarded
163 * 0xb0000000 256M PCI2 MEM Second half
164 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600165 .long FSL_BOOKE_MAS0(1, 4, 0)
166 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
Kumar Galac8c41d42008-01-16 10:04:42 -0600167 .long FSL_BOOKE_MAS2(CFG_PCI2_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
168 .long FSL_BOOKE_MAS3(CFG_PCI2_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100169
170 /*
171 * TLB 5: 64M Non-cacheable, guarded
172 * 0xe000_0000 1M CCSRBAR
173 * 0xe200_0000 16M PCI1 IO
174 * 0xe300_0000 16M PCI2 IO
175 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600176 .long FSL_BOOKE_MAS0(1, 5, 0)
177 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
178 .long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
179 .long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100180
181 /*
182 * TLB 6: 256M Non-cacheable, guarded
183 * 0xf0000000 Local bus expansion option.
184 * 0xfb000000 Configuration Latch register (one word)
185 * 0xfc000000 Up to 64M flash
186 */
Kumar Gala2146cf52007-12-19 01:18:15 -0600187 .long FSL_BOOKE_MAS0(1, 7, 0)
188 .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
189 .long FSL_BOOKE_MAS2(CFG_LBC_OPTION_BASE, (MAS2_I|MAS2_G))
190 .long FSL_BOOKE_MAS3(CFG_LBC_OPTION_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
Dan Malek35171dc2007-01-05 09:15:34 +0100191 entry_end