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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk281e00a2004-08-01 22:48:16 +00002/*
3 dm9000.c: Version 1.2 12/15/2003
4
5 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
6 Copyright (C) 1997 Sten Wang
7
wdenk281e00a2004-08-01 22:48:16 +00008 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
9
10V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
Wolfgang Denk53677ef2008-05-20 16:00:29 +020011 06/22/2001 Support DM9801 progrmming
12 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
13 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
14 R17 = (R17 & 0xfff0) | NF + 3
15 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
16 R17 = (R17 & 0xfff0) | NF
wdenk281e00a2004-08-01 22:48:16 +000017
Wolfgang Denk53677ef2008-05-20 16:00:29 +020018v1.00 modify by simon 2001.9.5
Wolfgang Denk93e14592013-10-04 17:43:24 +020019 change for kernel 2.4.x
wdenk281e00a2004-08-01 22:48:16 +000020
Wolfgang Denk53677ef2008-05-20 16:00:29 +020021v1.1 11/09/2001 fix force mode bug
wdenk281e00a2004-08-01 22:48:16 +000022
23v1.2 03/18/2003 Weilun Huang <weilun_huang@davicom.com.tw>:
24 Fixed phy reset.
25 Added tx/rx 32 bit mode.
26 Cleaned up for kernel merge.
27
28--------------------------------------
29
Remy Bohmera1013612008-06-03 15:26:21 +020030 12/15/2003 Initial port to u-boot by
Wolfgang Denk0cf207e2021-09-27 17:42:39 +020031 Sascha Hauer <saschahauer@web.de>
Remy Bohmera1013612008-06-03 15:26:21 +020032
33 06/03/2008 Remy Bohmer <linux@bohmer.net>
Remy Bohmer850ba752008-06-03 15:26:25 +020034 - Fixed the driver to work with DM9000A.
35 (check on ISR receive status bit before reading the
36 FIFO as described in DM9000 programming guide and
37 application notes)
Remy Bohmera1013612008-06-03 15:26:21 +020038 - Added autodetect of databus width.
Remy Bohmer134e2662008-06-03 15:26:22 +020039 - Made debug code compile again.
Remy Bohmeracba3182008-06-03 15:26:23 +020040 - Adapt eth_send such that it matches the DM9000*
41 application notes. Needed to make it work properly
42 for DM9000A.
Remy Bohmerfbcb7ec2008-06-03 15:26:24 +020043 - Adapted reset procedure to match DM9000 application
44 notes (i.e. double reset)
Remy Bohmer98291e22008-06-03 15:26:26 +020045 - some minor code cleanups
Remy Bohmera1013612008-06-03 15:26:21 +020046 These changes are tested with DM9000{A,EP,E} together
Remy Bohmere5a3bc22009-05-03 12:11:40 +020047 with a 200MHz Atmel AT91SAM9261 core
wdenk281e00a2004-08-01 22:48:16 +000048
Andrew Dyerd26b7392008-08-26 17:03:38 -050049TODO: external MII is not functional, only internal at the moment.
wdenk281e00a2004-08-01 22:48:16 +000050*/
51
52#include <common.h>
53#include <command.h>
54#include <net.h>
55#include <asm/io.h>
Remy Bohmere5a3bc22009-05-03 12:11:40 +020056#include <dm9000.h>
Simon Glassc05ed002020-05-10 11:40:11 -060057#include <linux/delay.h>
wdenk281e00a2004-08-01 22:48:16 +000058
wdenk281e00a2004-08-01 22:48:16 +000059#include "dm9000x.h"
60
61/* Board/System/Debug information/definition ---------------- */
62
wdenk281e00a2004-08-01 22:48:16 +000063/* #define CONFIG_DM9000_DEBUG */
64
65#ifdef CONFIG_DM9000_DEBUG
Remy Bohmer134e2662008-06-03 15:26:22 +020066#define DM9000_DBG(fmt,args...) printf(fmt, ##args)
67#define DM9000_DMP_PACKET(func,packet,length) \
68 do { \
Wolfgang Denk0cf207e2021-09-27 17:42:39 +020069 int i; \
Thomas Weber076cd242009-12-09 09:38:04 +010070 printf("%s: length: %d\n", func, length); \
Remy Bohmer134e2662008-06-03 15:26:22 +020071 for (i = 0; i < length; i++) { \
72 if (i % 8 == 0) \
73 printf("\n%s: %02x: ", func, i); \
74 printf("%02x ", ((unsigned char *) packet)[i]); \
75 } printf("\n"); \
76 } while(0)
77#else
wdenk281e00a2004-08-01 22:48:16 +000078#define DM9000_DBG(fmt,args...)
Remy Bohmer134e2662008-06-03 15:26:22 +020079#define DM9000_DMP_PACKET(func,packet,length)
80#endif
81
wdenk281e00a2004-08-01 22:48:16 +000082/* Structure/enum declaration ------------------------------- */
83typedef struct board_info {
84 u32 runt_length_counter; /* counter: RX length < 64byte */
85 u32 long_length_counter; /* counter: RX length > 1514byte */
86 u32 reset_counter; /* counter: RESET */
87 u32 reset_tx_timeout; /* RESET caused by TX Timeout */
88 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
89 u16 tx_pkt_cnt;
90 u16 queue_start_addr;
91 u16 dbug_cnt;
92 u8 phy_addr;
93 u8 device_wait_reset; /* device state */
wdenk281e00a2004-08-01 22:48:16 +000094 unsigned char srom[128];
Remy Bohmer0e38c932008-06-05 13:03:36 +020095 void (*outblk)(volatile void *data_ptr, int count);
Remy Bohmera1013612008-06-03 15:26:21 +020096 void (*inblk)(void *data_ptr, int count);
97 void (*rx_status)(u16 *RxStatus, u16 *RxLen);
Remy Bohmer60f61e62009-05-02 21:49:18 +020098 struct eth_device netdev;
Remy Bohmer98291e22008-06-03 15:26:26 +020099} board_info_t;
Remy Bohmera1013612008-06-03 15:26:21 +0200100static board_info_t dm9000_info;
wdenk281e00a2004-08-01 22:48:16 +0000101
Remy Bohmer60f61e62009-05-02 21:49:18 +0200102
wdenk281e00a2004-08-01 22:48:16 +0000103/* function declaration ------------------------------------- */
wdenk281e00a2004-08-01 22:48:16 +0000104static int dm9000_probe(void);
Andy Fleming09c04c22011-03-22 22:49:13 -0500105static u16 dm9000_phy_read(int);
106static void dm9000_phy_write(int, u16);
wdenk281e00a2004-08-01 22:48:16 +0000107static u8 DM9000_ior(int);
108static void DM9000_iow(int reg, u8 value);
109
110/* DM9000 network board routine ---------------------------- */
Jason Jin5c1d0822011-08-25 15:46:43 +0800111#ifndef CONFIG_DM9000_BYTE_SWAPPED
Mike Frysinger67bee2f2010-07-05 02:29:21 -0400112#define DM9000_outb(d,r) writeb(d, (volatile u8 *)(r))
113#define DM9000_outw(d,r) writew(d, (volatile u16 *)(r))
114#define DM9000_outl(d,r) writel(d, (volatile u32 *)(r))
115#define DM9000_inb(r) readb((volatile u8 *)(r))
116#define DM9000_inw(r) readw((volatile u16 *)(r))
117#define DM9000_inl(r) readl((volatile u32 *)(r))
Jason Jin5c1d0822011-08-25 15:46:43 +0800118#else
119#define DM9000_outb(d, r) __raw_writeb(d, r)
120#define DM9000_outw(d, r) __raw_writew(d, r)
121#define DM9000_outl(d, r) __raw_writel(d, r)
122#define DM9000_inb(r) __raw_readb(r)
123#define DM9000_inw(r) __raw_readw(r)
124#define DM9000_inl(r) __raw_readl(r)
125#endif
wdenk281e00a2004-08-01 22:48:16 +0000126
127#ifdef CONFIG_DM9000_DEBUG
128static void
129dump_regs(void)
130{
131 DM9000_DBG("\n");
132 DM9000_DBG("NCR (0x00): %02x\n", DM9000_ior(0));
133 DM9000_DBG("NSR (0x01): %02x\n", DM9000_ior(1));
134 DM9000_DBG("TCR (0x02): %02x\n", DM9000_ior(2));
135 DM9000_DBG("TSRI (0x03): %02x\n", DM9000_ior(3));
136 DM9000_DBG("TSRII (0x04): %02x\n", DM9000_ior(4));
137 DM9000_DBG("RCR (0x05): %02x\n", DM9000_ior(5));
138 DM9000_DBG("RSR (0x06): %02x\n", DM9000_ior(6));
Remy Bohmer134e2662008-06-03 15:26:22 +0200139 DM9000_DBG("ISR (0xFE): %02x\n", DM9000_ior(DM9000_ISR));
wdenk281e00a2004-08-01 22:48:16 +0000140 DM9000_DBG("\n");
141}
Remy Bohmera1013612008-06-03 15:26:21 +0200142#endif
143
Remy Bohmer0e38c932008-06-05 13:03:36 +0200144static void dm9000_outblk_8bit(volatile void *data_ptr, int count)
Remy Bohmera1013612008-06-03 15:26:21 +0200145{
146 int i;
147 for (i = 0; i < count; i++)
148 DM9000_outb((((u8 *) data_ptr)[i] & 0xff), DM9000_DATA);
149}
150
Remy Bohmer0e38c932008-06-05 13:03:36 +0200151static void dm9000_outblk_16bit(volatile void *data_ptr, int count)
Remy Bohmera1013612008-06-03 15:26:21 +0200152{
153 int i;
154 u32 tmplen = (count + 1) / 2;
155
156 for (i = 0; i < tmplen; i++)
157 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
158}
Remy Bohmer0e38c932008-06-05 13:03:36 +0200159static void dm9000_outblk_32bit(volatile void *data_ptr, int count)
Remy Bohmera1013612008-06-03 15:26:21 +0200160{
161 int i;
162 u32 tmplen = (count + 3) / 4;
163
164 for (i = 0; i < tmplen; i++)
165 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
166}
167
168static void dm9000_inblk_8bit(void *data_ptr, int count)
169{
170 int i;
171 for (i = 0; i < count; i++)
172 ((u8 *) data_ptr)[i] = DM9000_inb(DM9000_DATA);
173}
174
175static void dm9000_inblk_16bit(void *data_ptr, int count)
176{
177 int i;
178 u32 tmplen = (count + 1) / 2;
179
180 for (i = 0; i < tmplen; i++)
181 ((u16 *) data_ptr)[i] = DM9000_inw(DM9000_DATA);
182}
183static void dm9000_inblk_32bit(void *data_ptr, int count)
184{
185 int i;
186 u32 tmplen = (count + 3) / 4;
187
188 for (i = 0; i < tmplen; i++)
189 ((u32 *) data_ptr)[i] = DM9000_inl(DM9000_DATA);
190}
191
192static void dm9000_rx_status_32bit(u16 *RxStatus, u16 *RxLen)
193{
Remy Bohmerd6ee5fa2008-06-04 10:47:25 +0200194 u32 tmpdata;
Remy Bohmera1013612008-06-03 15:26:21 +0200195
196 DM9000_outb(DM9000_MRCMD, DM9000_IO);
197
Remy Bohmerd6ee5fa2008-06-04 10:47:25 +0200198 tmpdata = DM9000_inl(DM9000_DATA);
TsiChung Liew943b8252008-06-25 15:48:52 -0500199 *RxStatus = __le16_to_cpu(tmpdata);
200 *RxLen = __le16_to_cpu(tmpdata >> 16);
Remy Bohmera1013612008-06-03 15:26:21 +0200201}
202
203static void dm9000_rx_status_16bit(u16 *RxStatus, u16 *RxLen)
204{
205 DM9000_outb(DM9000_MRCMD, DM9000_IO);
206
TsiChung Liew943b8252008-06-25 15:48:52 -0500207 *RxStatus = __le16_to_cpu(DM9000_inw(DM9000_DATA));
208 *RxLen = __le16_to_cpu(DM9000_inw(DM9000_DATA));
Remy Bohmera1013612008-06-03 15:26:21 +0200209}
210
211static void dm9000_rx_status_8bit(u16 *RxStatus, u16 *RxLen)
212{
213 DM9000_outb(DM9000_MRCMD, DM9000_IO);
214
TsiChung Liew943b8252008-06-25 15:48:52 -0500215 *RxStatus =
216 __le16_to_cpu(DM9000_inb(DM9000_DATA) +
217 (DM9000_inb(DM9000_DATA) << 8));
218 *RxLen =
219 __le16_to_cpu(DM9000_inb(DM9000_DATA) +
220 (DM9000_inb(DM9000_DATA) << 8));
Remy Bohmera1013612008-06-03 15:26:21 +0200221}
wdenk281e00a2004-08-01 22:48:16 +0000222
223/*
224 Search DM9000 board, allocate space and register it
225*/
226int
227dm9000_probe(void)
228{
229 u32 id_val;
230 id_val = DM9000_ior(DM9000_VIDL);
231 id_val |= DM9000_ior(DM9000_VIDH) << 8;
232 id_val |= DM9000_ior(DM9000_PIDL) << 16;
233 id_val |= DM9000_ior(DM9000_PIDH) << 24;
234 if (id_val == DM9000_ID) {
235 printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
236 id_val);
237 return 0;
238 } else {
239 printf("dm9000 not found at 0x%08x id: 0x%08x\n",
240 CONFIG_DM9000_BASE, id_val);
241 return -1;
242 }
243}
244
wdenk281e00a2004-08-01 22:48:16 +0000245/* General Purpose dm9000 reset routine */
246static void
247dm9000_reset(void)
248{
Remy Bohmerfbcb7ec2008-06-03 15:26:24 +0200249 DM9000_DBG("resetting DM9000\n");
250
251 /* Reset DM9000,
252 see DM9000 Application Notes V1.22 Jun 11, 2004 page 29 */
253
Andrew Dyerd26b7392008-08-26 17:03:38 -0500254 /* DEBUG: Make all GPIO0 outputs, all others inputs */
255 DM9000_iow(DM9000_GPCR, GPCR_GPIO0_OUT);
Remy Bohmerfbcb7ec2008-06-03 15:26:24 +0200256 /* Step 1: Power internal PHY by writing 0 to GPIO0 pin */
257 DM9000_iow(DM9000_GPR, 0);
258 /* Step 2: Software reset */
Andrew Dyerd26b7392008-08-26 17:03:38 -0500259 DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST));
Remy Bohmerfbcb7ec2008-06-03 15:26:24 +0200260
261 do {
262 DM9000_DBG("resetting the DM9000, 1st reset\n");
263 udelay(25); /* Wait at least 20 us */
264 } while (DM9000_ior(DM9000_NCR) & 1);
265
266 DM9000_iow(DM9000_NCR, 0);
Andrew Dyerd26b7392008-08-26 17:03:38 -0500267 DM9000_iow(DM9000_NCR, (NCR_LBK_INT_MAC | NCR_RST)); /* Issue a second reset */
Remy Bohmerfbcb7ec2008-06-03 15:26:24 +0200268
269 do {
270 DM9000_DBG("resetting the DM9000, 2nd reset\n");
271 udelay(25); /* Wait at least 20 us */
272 } while (DM9000_ior(DM9000_NCR) & 1);
273
274 /* Check whether the ethernet controller is present */
275 if ((DM9000_ior(DM9000_PIDL) != 0x0) ||
276 (DM9000_ior(DM9000_PIDH) != 0x90))
277 printf("ERROR: resetting DM9000 -> not responding\n");
wdenk281e00a2004-08-01 22:48:16 +0000278}
279
Remy Bohmer60f61e62009-05-02 21:49:18 +0200280/* Initialize dm9000 board
wdenk281e00a2004-08-01 22:48:16 +0000281*/
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900282static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
wdenk281e00a2004-08-01 22:48:16 +0000283{
284 int i, oft, lnk;
Remy Bohmera1013612008-06-03 15:26:21 +0200285 u8 io_mode;
286 struct board_info *db = &dm9000_info;
287
Remy Bohmer60f61e62009-05-02 21:49:18 +0200288 DM9000_DBG("%s\n", __func__);
wdenk281e00a2004-08-01 22:48:16 +0000289
290 /* RESET device */
291 dm9000_reset();
Andrew Dyerd26b7392008-08-26 17:03:38 -0500292
293 if (dm9000_probe() < 0)
294 return -1;
wdenk281e00a2004-08-01 22:48:16 +0000295
Remy Bohmera1013612008-06-03 15:26:21 +0200296 /* Auto-detect 8/16/32 bit mode, ISR Bit 6+7 indicate bus width */
297 io_mode = DM9000_ior(DM9000_ISR) >> 6;
298
299 switch (io_mode) {
300 case 0x0: /* 16-bit mode */
301 printf("DM9000: running in 16 bit mode\n");
302 db->outblk = dm9000_outblk_16bit;
303 db->inblk = dm9000_inblk_16bit;
304 db->rx_status = dm9000_rx_status_16bit;
305 break;
306 case 0x01: /* 32-bit mode */
307 printf("DM9000: running in 32 bit mode\n");
308 db->outblk = dm9000_outblk_32bit;
309 db->inblk = dm9000_inblk_32bit;
310 db->rx_status = dm9000_rx_status_32bit;
311 break;
312 case 0x02: /* 8 bit mode */
313 printf("DM9000: running in 8 bit mode\n");
314 db->outblk = dm9000_outblk_8bit;
315 db->inblk = dm9000_inblk_8bit;
316 db->rx_status = dm9000_rx_status_8bit;
317 break;
318 default:
319 /* Assume 8 bit mode, will probably not work anyway */
320 printf("DM9000: Undefined IO-mode:0x%x\n", io_mode);
321 db->outblk = dm9000_outblk_8bit;
322 db->inblk = dm9000_inblk_8bit;
323 db->rx_status = dm9000_rx_status_8bit;
324 break;
325 }
326
Andrew Dyerd26b7392008-08-26 17:03:38 -0500327 /* Program operating register, only internal phy supported */
Remy Bohmer98291e22008-06-03 15:26:26 +0200328 DM9000_iow(DM9000_NCR, 0x0);
329 /* TX Polling clear */
330 DM9000_iow(DM9000_TCR, 0);
331 /* Less 3Kb, 200us */
Andrew Dyerd26b7392008-08-26 17:03:38 -0500332 DM9000_iow(DM9000_BPTR, BPTR_BPHW(3) | BPTR_JPT_600US);
Remy Bohmer98291e22008-06-03 15:26:26 +0200333 /* Flow Control : High/Low Water */
334 DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8));
335 /* SH FIXME: This looks strange! Flow Control */
336 DM9000_iow(DM9000_FCR, 0x0);
337 /* Special Mode */
338 DM9000_iow(DM9000_SMCR, 0);
339 /* clear TX status */
340 DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END);
341 /* Clear interrupt status */
Andrew Dyerd26b7392008-08-26 17:03:38 -0500342 DM9000_iow(DM9000_ISR, ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS);
wdenk281e00a2004-08-01 22:48:16 +0000343
Ben Warren07754372009-10-21 21:53:39 -0700344 printf("MAC: %pM\n", dev->enetaddr);
Joe Hershberger0adb5b72015-04-08 01:41:04 -0500345 if (!is_valid_ethaddr(dev->enetaddr)) {
Andrew Ruderc583ee12013-10-22 19:09:02 -0500346 printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
Andrew Ruderc583ee12013-10-22 19:09:02 -0500347 }
Andrew Dyerd26b7392008-08-26 17:03:38 -0500348
349 /* fill device MAC address registers */
350 for (i = 0, oft = DM9000_PAR; i < 6; i++, oft++)
Ben Warren07754372009-10-21 21:53:39 -0700351 DM9000_iow(oft, dev->enetaddr[i]);
wdenk281e00a2004-08-01 22:48:16 +0000352 for (i = 0, oft = 0x16; i < 8; i++, oft++)
353 DM9000_iow(oft, 0xff);
354
355 /* read back mac, just to be sure */
356 for (i = 0, oft = 0x10; i < 6; i++, oft++)
357 DM9000_DBG("%02x:", DM9000_ior(oft));
358 DM9000_DBG("\n");
359
360 /* Activate DM9000 */
Remy Bohmer98291e22008-06-03 15:26:26 +0200361 /* RX enable */
362 DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);
363 /* Enable TX/RX interrupt mask */
364 DM9000_iow(DM9000_IMR, IMR_PAR);
365
wdenk281e00a2004-08-01 22:48:16 +0000366 i = 0;
Andy Fleming09c04c22011-03-22 22:49:13 -0500367 while (!(dm9000_phy_read(1) & 0x20)) { /* autonegation complete bit */
wdenk281e00a2004-08-01 22:48:16 +0000368 udelay(1000);
369 i++;
370 if (i == 10000) {
371 printf("could not establish link\n");
372 return 0;
373 }
374 }
375
376 /* see what we've got */
Andy Fleming09c04c22011-03-22 22:49:13 -0500377 lnk = dm9000_phy_read(17) >> 12;
wdenk281e00a2004-08-01 22:48:16 +0000378 printf("operating at ");
379 switch (lnk) {
380 case 1:
381 printf("10M half duplex ");
382 break;
383 case 2:
384 printf("10M full duplex ");
385 break;
386 case 4:
387 printf("100M half duplex ");
388 break;
389 case 8:
390 printf("100M full duplex ");
391 break;
392 default:
393 printf("unknown: %d ", lnk);
394 break;
395 }
396 printf("mode\n");
397 return 0;
398}
399
400/*
401 Hardware start transmission.
402 Send a packet to media from the upper layer.
403*/
Joe Hershberger7f9a8a62012-05-21 14:45:23 +0000404static int dm9000_send(struct eth_device *netdev, void *packet, int length)
wdenk281e00a2004-08-01 22:48:16 +0000405{
wdenk281e00a2004-08-01 22:48:16 +0000406 int tmo;
Remy Bohmera1013612008-06-03 15:26:21 +0200407 struct board_info *db = &dm9000_info;
408
Remy Bohmer60f61e62009-05-02 21:49:18 +0200409 DM9000_DMP_PACKET(__func__ , packet, length);
wdenk281e00a2004-08-01 22:48:16 +0000410
Remy Bohmeracba3182008-06-03 15:26:23 +0200411 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
412
wdenk281e00a2004-08-01 22:48:16 +0000413 /* Move data to DM9000 TX RAM */
Remy Bohmeracba3182008-06-03 15:26:23 +0200414 DM9000_outb(DM9000_MWCMD, DM9000_IO); /* Prepare for TX-data */
wdenk281e00a2004-08-01 22:48:16 +0000415
Remy Bohmera1013612008-06-03 15:26:21 +0200416 /* push the data to the TX-fifo */
Remy Bohmer0e38c932008-06-05 13:03:36 +0200417 (db->outblk)(packet, length);
wdenk281e00a2004-08-01 22:48:16 +0000418
419 /* Set TX length to DM9000 */
420 DM9000_iow(DM9000_TXPLL, length & 0xff);
421 DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
422
423 /* Issue TX polling command */
Remy Bohmeracba3182008-06-03 15:26:23 +0200424 DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
wdenk281e00a2004-08-01 22:48:16 +0000425
426 /* wait for end of transmission */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
Remy Bohmeracba3182008-06-03 15:26:23 +0200428 while ( !(DM9000_ior(DM9000_NSR) & (NSR_TX1END | NSR_TX2END)) ||
429 !(DM9000_ior(DM9000_ISR) & IMR_PTM) ) {
wdenk281e00a2004-08-01 22:48:16 +0000430 if (get_timer(0) >= tmo) {
431 printf("transmission timeout\n");
432 break;
433 }
434 }
Remy Bohmeracba3182008-06-03 15:26:23 +0200435 DM9000_iow(DM9000_ISR, IMR_PTM); /* Clear Tx bit in ISR */
436
wdenk281e00a2004-08-01 22:48:16 +0000437 DM9000_DBG("transmit done\n\n");
438 return 0;
439}
440
441/*
442 Stop the interface.
443 The interface is stopped when it is brought.
444*/
Remy Bohmer60f61e62009-05-02 21:49:18 +0200445static void dm9000_halt(struct eth_device *netdev)
wdenk281e00a2004-08-01 22:48:16 +0000446{
Remy Bohmer60f61e62009-05-02 21:49:18 +0200447 DM9000_DBG("%s\n", __func__);
wdenk281e00a2004-08-01 22:48:16 +0000448
449 /* RESET devie */
Andy Fleming09c04c22011-03-22 22:49:13 -0500450 dm9000_phy_write(0, 0x8000); /* PHY RESET */
wdenk281e00a2004-08-01 22:48:16 +0000451 DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
452 DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
453 DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
454}
455
456/*
457 Received a packet and pass to upper layer
458*/
Remy Bohmer60f61e62009-05-02 21:49:18 +0200459static int dm9000_rx(struct eth_device *netdev)
wdenk281e00a2004-08-01 22:48:16 +0000460{
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500461 u8 rxbyte;
462 u8 *rdptr = (u8 *)net_rx_packets[0];
wdenk281e00a2004-08-01 22:48:16 +0000463 u16 RxStatus, RxLen = 0;
Remy Bohmera1013612008-06-03 15:26:21 +0200464 struct board_info *db = &dm9000_info;
wdenk281e00a2004-08-01 22:48:16 +0000465
Remy Bohmer850ba752008-06-03 15:26:25 +0200466 /* Check packet ready or not, we must check
467 the ISR status first for DM9000A */
468 if (!(DM9000_ior(DM9000_ISR) & 0x01)) /* Rx-ISR bit must be set. */
wdenk281e00a2004-08-01 22:48:16 +0000469 return 0;
470
Remy Bohmer850ba752008-06-03 15:26:25 +0200471 DM9000_iow(DM9000_ISR, 0x01); /* clear PR status latched in bit 0 */
wdenk281e00a2004-08-01 22:48:16 +0000472
Remy Bohmer850ba752008-06-03 15:26:25 +0200473 /* There is _at least_ 1 package in the fifo, read them all */
474 for (;;) {
475 DM9000_ior(DM9000_MRCMDX); /* Dummy read */
wdenk281e00a2004-08-01 22:48:16 +0000476
Remy Bohmer0e38c932008-06-05 13:03:36 +0200477 /* Get most updated data,
478 only look at bits 0:1, See application notes DM9000 */
479 rxbyte = DM9000_inb(DM9000_DATA) & 0x03;
wdenk281e00a2004-08-01 22:48:16 +0000480
Remy Bohmer850ba752008-06-03 15:26:25 +0200481 /* Status check: this byte must be 0 or 1 */
482 if (rxbyte > DM9000_PKT_RDY) {
483 DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
484 DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
485 printf("DM9000 error: status check fail: 0x%x\n",
486 rxbyte);
487 return 0;
wdenk281e00a2004-08-01 22:48:16 +0000488 }
wdenk281e00a2004-08-01 22:48:16 +0000489
Remy Bohmer850ba752008-06-03 15:26:25 +0200490 if (rxbyte != DM9000_PKT_RDY)
491 return 0; /* No packet received, ignore */
492
493 DM9000_DBG("receiving packet\n");
494
495 /* A packet ready now & Get status/length */
496 (db->rx_status)(&RxStatus, &RxLen);
497
498 DM9000_DBG("rx status: 0x%04x rx len: %d\n", RxStatus, RxLen);
499
500 /* Move data from DM9000 */
501 /* Read received packet from RX SRAM */
502 (db->inblk)(rdptr, RxLen);
503
504 if ((RxStatus & 0xbf00) || (RxLen < 0x40)
505 || (RxLen > DM9000_PKT_MAX)) {
506 if (RxStatus & 0x100) {
507 printf("rx fifo error\n");
508 }
509 if (RxStatus & 0x200) {
510 printf("rx crc error\n");
511 }
512 if (RxStatus & 0x8000) {
513 printf("rx length error\n");
514 }
515 if (RxLen > DM9000_PKT_MAX) {
516 printf("rx length too big\n");
517 dm9000_reset();
518 }
519 } else {
Remy Bohmer60f61e62009-05-02 21:49:18 +0200520 DM9000_DMP_PACKET(__func__ , rdptr, RxLen);
Remy Bohmer850ba752008-06-03 15:26:25 +0200521
522 DM9000_DBG("passing packet to upper layer\n");
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500523 net_process_received_packet(net_rx_packets[0], RxLen);
Remy Bohmer850ba752008-06-03 15:26:25 +0200524 }
wdenk281e00a2004-08-01 22:48:16 +0000525 }
526 return 0;
527}
528
529/*
530 Read a word data from SROM
531*/
Remy Bohmere5a3bc22009-05-03 12:11:40 +0200532#if !defined(CONFIG_DM9000_NO_SROM)
533void dm9000_read_srom_word(int offset, u8 *to)
wdenk281e00a2004-08-01 22:48:16 +0000534{
535 DM9000_iow(DM9000_EPAR, offset);
536 DM9000_iow(DM9000_EPCR, 0x4);
stefano babic5f470942007-08-21 15:50:33 +0200537 udelay(8000);
wdenk281e00a2004-08-01 22:48:16 +0000538 DM9000_iow(DM9000_EPCR, 0x0);
David Brownellad74cae2009-04-16 23:15:15 -0700539 to[0] = DM9000_ior(DM9000_EPDRL);
540 to[1] = DM9000_ior(DM9000_EPDRH);
wdenk281e00a2004-08-01 22:48:16 +0000541}
542
Remy Bohmere5a3bc22009-05-03 12:11:40 +0200543void dm9000_write_srom_word(int offset, u16 val)
stefano babic5e5803e2007-08-30 23:01:49 +0200544{
545 DM9000_iow(DM9000_EPAR, offset);
546 DM9000_iow(DM9000_EPDRH, ((val >> 8) & 0xff));
547 DM9000_iow(DM9000_EPDRL, (val & 0xff));
548 DM9000_iow(DM9000_EPCR, 0x12);
549 udelay(8000);
550 DM9000_iow(DM9000_EPCR, 0);
551}
Remy Bohmere5a3bc22009-05-03 12:11:40 +0200552#endif
stefano babic5e5803e2007-08-30 23:01:49 +0200553
Ben Warren07754372009-10-21 21:53:39 -0700554static void dm9000_get_enetaddr(struct eth_device *dev)
555{
556#if !defined(CONFIG_DM9000_NO_SROM)
557 int i;
558 for (i = 0; i < 3; i++)
559 dm9000_read_srom_word(i, dev->enetaddr + (2 * i));
560#endif
561}
562
wdenk281e00a2004-08-01 22:48:16 +0000563/*
564 Read a byte from I/O port
565*/
566static u8
567DM9000_ior(int reg)
568{
569 DM9000_outb(reg, DM9000_IO);
570 return DM9000_inb(DM9000_DATA);
571}
572
573/*
574 Write a byte to I/O port
575*/
576static void
577DM9000_iow(int reg, u8 value)
578{
579 DM9000_outb(reg, DM9000_IO);
580 DM9000_outb(value, DM9000_DATA);
581}
582
583/*
584 Read a word from phyxcer
585*/
586static u16
Andy Fleming09c04c22011-03-22 22:49:13 -0500587dm9000_phy_read(int reg)
wdenk281e00a2004-08-01 22:48:16 +0000588{
589 u16 val;
590
591 /* Fill the phyxcer register into REG_0C */
592 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
593 DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
Remy Bohmer98291e22008-06-03 15:26:26 +0200594 udelay(100); /* Wait read complete */
wdenk281e00a2004-08-01 22:48:16 +0000595 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
596 val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
597
598 /* The read data keeps on REG_0D & REG_0E */
Andy Fleming09c04c22011-03-22 22:49:13 -0500599 DM9000_DBG("dm9000_phy_read(0x%x): 0x%x\n", reg, val);
wdenk281e00a2004-08-01 22:48:16 +0000600 return val;
601}
602
603/*
604 Write a word to phyxcer
605*/
606static void
Andy Fleming09c04c22011-03-22 22:49:13 -0500607dm9000_phy_write(int reg, u16 value)
wdenk281e00a2004-08-01 22:48:16 +0000608{
609
610 /* Fill the phyxcer register into REG_0C */
611 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
612
613 /* Fill the written data into REG_0D & REG_0E */
614 DM9000_iow(DM9000_EPDRL, (value & 0xff));
615 DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
616 DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
Remy Bohmer98291e22008-06-03 15:26:26 +0200617 udelay(500); /* Wait write complete */
wdenk281e00a2004-08-01 22:48:16 +0000618 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
Andy Fleming09c04c22011-03-22 22:49:13 -0500619 DM9000_DBG("dm9000_phy_write(reg:0x%x, value:0x%x)\n", reg, value);
wdenk281e00a2004-08-01 22:48:16 +0000620}
Remy Bohmer60f61e62009-05-02 21:49:18 +0200621
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900622int dm9000_initialize(struct bd_info *bis)
Remy Bohmer60f61e62009-05-02 21:49:18 +0200623{
624 struct eth_device *dev = &(dm9000_info.netdev);
625
Ben Warren07754372009-10-21 21:53:39 -0700626 /* Load MAC address from EEPROM */
627 dm9000_get_enetaddr(dev);
628
Remy Bohmer60f61e62009-05-02 21:49:18 +0200629 dev->init = dm9000_init;
630 dev->halt = dm9000_halt;
631 dev->send = dm9000_send;
632 dev->recv = dm9000_rx;
Ben Whitten192bc692015-12-30 13:05:58 +0000633 strcpy(dev->name, "dm9000");
Remy Bohmer60f61e62009-05-02 21:49:18 +0200634
635 eth_register(dev);
636
637 return 0;
638}