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wdenk16f21702002-08-26 21:58:50 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 *
24 * Modified By Conn Clark to work with Esteem 192E 7/31/00
25 *
26 */
27
28#include <common.h>
29#include <mpc8xx.h>
30
31/* ------------------------------------------------------------------------- */
32
wdenk16f21702002-08-26 21:58:50 +000033#define _NOT_USED_ 0xFFFFFFFF
34
wdenkc83bf6a2004-01-06 22:38:14 +000035const uint sdram_table[] = {
wdenk16f21702002-08-26 21:58:50 +000036 /*
37 * Single Read. (Offset 0 in UPMA RAM)
38 *
39 * active, NOP, read, precharge, NOP */
40 0x0F27CC04, 0x0EAECC04, 0x00B98C04, 0x00F74C00,
wdenkc83bf6a2004-01-06 22:38:14 +000041 0x11FFCC05, /* last */
wdenk16f21702002-08-26 21:58:50 +000042 /*
43 * SDRAM Initialization (offset 5 in UPMA RAM)
44 *
wdenk8bde7f72003-06-27 21:31:46 +000045 * This is no UPM entry point. The following definition uses
46 * the remaining space to establish an initialization
47 * sequence, which is executed by a RUN command.
wdenk16f21702002-08-26 21:58:50 +000048 * NOP, Program
49 */
wdenkc83bf6a2004-01-06 22:38:14 +000050 0x0F0A8C34, 0x1F354C37, /* last */
wdenk16f21702002-08-26 21:58:50 +000051
wdenkc83bf6a2004-01-06 22:38:14 +000052 _NOT_USED_, /* Not used */
wdenk16f21702002-08-26 21:58:50 +000053
54 /*
55 * Burst Read. (Offset 8 in UPMA RAM)
56 * active, NOP, read, NOP, NOP, NOP, NOP, NOP */
57 0x0F37CC04, 0x0EFECC04, 0x00FDCC04, 0x00FFCC00,
wdenkc83bf6a2004-01-06 22:38:14 +000058 0x00FFCC00, 0x01FFCC00, 0x0FFFCC00, 0x1FFFCC05, /* last */
wdenk16f21702002-08-26 21:58:50 +000059 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
61 /*
62 * Single Write. (Offset 18 in UPMA RAM)
63 * active, NOP, write, NOP, precharge, NOP */
64 0x0F27CC04, 0x0EAE8C00, 0x01BD4C04, 0x0FFB8C04,
wdenkc83bf6a2004-01-06 22:38:14 +000065 0x0FF74C04, 0x1FFFCC05, /* last */
wdenk16f21702002-08-26 21:58:50 +000066 _NOT_USED_, _NOT_USED_,
67 /*
68 * Burst Write. (Offset 20 in UPMA RAM)
69 * active, NOP, write, NOP, NOP, NOP, NOP, NOP */
70 0x0F37CC04, 0x0EFE8C00, 0x00FD4C00, 0x00FFCC00,
wdenkc83bf6a2004-01-06 22:38:14 +000071 0x00FFCC00, 0x01FFCC04, 0x0FFFCC04, 0x1FFFCC05, /* last */
wdenk16f21702002-08-26 21:58:50 +000072 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 /*
75 * Refresh (Offset 30 in UPMA RAM)
76 * precharge, NOP, auto_ref, NOP, NOP, NOP */
77 0x0FF74C34, 0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34,
wdenkc83bf6a2004-01-06 22:38:14 +000078 0x0FFFCCB4, 0x1FFFCC35, /* last */
79 _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +000080 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 /*
82 * Exception. (Offset 3c in UPMA RAM)
83 */
wdenkc83bf6a2004-01-06 22:38:14 +000084 0x0FFB8C00, 0x1FF74C03, /* last */
85 _NOT_USED_, _NOT_USED_
wdenk16f21702002-08-26 21:58:50 +000086};
87
88/* ------------------------------------------------------------------------- */
89
90
91/*
92 * Check Board Identity:
93 */
94
95int checkboard (void)
96{
wdenkc83bf6a2004-01-06 22:38:14 +000097 puts ("Board: Esteem 192E\n");
98 return (0);
wdenk16f21702002-08-26 21:58:50 +000099}
100
101/* ------------------------------------------------------------------------- */
102
103
Becky Bruce9973e3c2008-06-09 16:03:40 -0500104phys_size_t initdram (int board_type)
wdenk16f21702002-08-26 21:58:50 +0000105{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc83bf6a2004-01-06 22:38:14 +0000107 volatile memctl8xx_t *memctl = &immap->im_memctl;
108 long int size_b0, size_b1;
wdenk16f21702002-08-26 21:58:50 +0000109
wdenkc83bf6a2004-01-06 22:38:14 +0000110 /*
111 * Explain frequency of refresh here
112 */
wdenk16f21702002-08-26 21:58:50 +0000113
wdenkc83bf6a2004-01-06 22:38:14 +0000114 memctl->memc_mptpr = 0x0200; /* divide by 32 */
wdenk16f21702002-08-26 21:58:50 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116 memctl->memc_mamr = 0x18003112; /*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
wdenk16f21702002-08-26 21:58:50 +0000117
wdenkc83bf6a2004-01-06 22:38:14 +0000118 upmconfig (UPMA, (uint *) sdram_table,
119 sizeof (sdram_table) / sizeof (uint));
wdenk16f21702002-08-26 21:58:50 +0000120
wdenkc83bf6a2004-01-06 22:38:14 +0000121 /*
122 * Map cs 2 and 3 to the SDRAM banks 0 and 1 at
123 * preliminary addresses - these have to be modified after the
124 * SDRAM size has been determined.
125 */
wdenk16f21702002-08-26 21:58:50 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */
128 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
wdenk16f21702002-08-26 21:58:50 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
131 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
wdenk16f21702002-08-26 21:58:50 +0000132
133
wdenkc83bf6a2004-01-06 22:38:14 +0000134 /* perform SDRAM initializsation sequence */
135 memctl->memc_mar = 0x00000088;
136 memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
137 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
wdenk16f21702002-08-26 21:58:50 +0000138
wdenkc83bf6a2004-01-06 22:38:14 +0000139 memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
140 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
wdenk16f21702002-08-26 21:58:50 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
wdenk16f21702002-08-26 21:58:50 +0000143
144/* printf ("banks 0 and 1 are programed\n"); */
145
wdenkc83bf6a2004-01-06 22:38:14 +0000146 /*
147 * Check Bank 0 Memory Size for re-configuration
148 *
149 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200150 size_b0 = get_ram_size ( (long *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
151 size_b1 = get_ram_size ( (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
wdenk16f21702002-08-26 21:58:50 +0000152
wdenkc83bf6a2004-01-06 22:38:14 +0000153 printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
wdenk16f21702002-08-26 21:58:50 +0000154
155/* printf ("bank 1 size %u\n",size_b1); */
156
wdenkc83bf6a2004-01-06 22:38:14 +0000157 if (size_b1 == 0) {
158 /*
159 * Adjust refresh rate if bank 0 isn't stuffed
160 */
161 memctl->memc_mptpr = 0x0400; /* divide by 64 */
162 memctl->memc_br3 &= 0x0FFFFFFFE;
wdenk16f21702002-08-26 21:58:50 +0000163
wdenkc83bf6a2004-01-06 22:38:14 +0000164 /*
165 * Adjust OR2 for size of bank 0
166 */
167 memctl->memc_or2 |= 7 * size_b0;
168 } else {
169 if (size_b0 < size_b1) {
170 memctl->memc_br2 &= 0x00007FFE;
171 memctl->memc_br3 &= 0x00007FFF;
wdenk16f21702002-08-26 21:58:50 +0000172
wdenkc83bf6a2004-01-06 22:38:14 +0000173 /*
174 * Adjust OR3 for size of bank 1
175 */
176 memctl->memc_or3 |= 15 * size_b1;
wdenk16f21702002-08-26 21:58:50 +0000177
wdenkc83bf6a2004-01-06 22:38:14 +0000178 /*
179 * Adjust OR2 for size of bank 0
180 */
181 memctl->memc_or2 |= 15 * size_b0;
182 memctl->memc_br2 += (size_b1 + 1);
183 } else {
184 memctl->memc_br3 &= 0x00007FFE;
wdenk16f21702002-08-26 21:58:50 +0000185
wdenkc83bf6a2004-01-06 22:38:14 +0000186 /*
187 * Adjust OR2 for size of bank 0
188 */
189 memctl->memc_or2 |= 15 * size_b0;
wdenk16f21702002-08-26 21:58:50 +0000190
wdenkc83bf6a2004-01-06 22:38:14 +0000191 /*
192 * Adjust OR3 for size of bank 1
193 */
194 memctl->memc_or3 |= 15 * size_b1;
195 memctl->memc_br3 += (size_b0 + 1);
196 }
wdenk16f21702002-08-26 21:58:50 +0000197 }
wdenkc83bf6a2004-01-06 22:38:14 +0000198
199 /* before leaving set all unused i/o pins to outputs */
200
201 /*
202 * --*Unused Pin List*--
203 *
204 * group/port bit number
205 * IP_B 0,1,3,4,5 Taken care of in pcmcia-cs-x.x.xx
206 * PA 5,7,8,9,14,15
207 * PB 22,23,31
208 * PC 4,5,6,7,10,11,12,13,14,15
209 * PD 5,6,7
210 *
211 */
212
213 /*
214 * --*Pin Used for I/O List*--
215 *
216 * port input bit number output bit number either
217 * PB 18,26,27
218 * PD 3,4 8,9,10,11,12,13,14,15
219 *
220 */
221
222 immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
223 immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
224 immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
225 immap->im_ioport.iop_padat |= 0x05C3; /* set unused pins as high */
226
227 immap->im_cpm.cp_pbpar &= ~0x00001331; /* set unused port b pins as io */
228 immap->im_cpm.cp_pbdir |= 0x00001331; /* set unused port b pins as output */
229 immap->im_cpm.cp_pbodr &= ~0x00001331; /* config bits 18,22,23,26,27 & 31 as normal outputs */
230 immap->im_cpm.cp_pbdat |= 0x00001331; /* set T/E LED, /NV_CS, & /POWER_ADJ_CS and the rest to a high */
231
232 immap->im_ioport.iop_pcpar &= ~0x0F3F; /* set unused port c pins as io */
233 immap->im_ioport.iop_pcdir |= 0x0F3F; /* set unused port c pins as output */
234 immap->im_ioport.iop_pcso &= ~0x0F3F; /* clear special purpose bit for unused port c pins for clarity */
235 immap->im_ioport.iop_pcdat |= 0x0F3F; /* set unused port c pins high */
236
237 immap->im_ioport.iop_pdpar &= 0xE000; /* set pins as io */
238 immap->im_ioport.iop_pddir &= 0xE000; /* set bit 3 & 4 as inputs */
239 immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
240 immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
241
242 return (size_b0 + size_b1);
wdenk16f21702002-08-26 21:58:50 +0000243}