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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Priyanka Jain062ef1a2013-10-18 17:19:06 +05302/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
Priyanka Jain062ef1a2013-10-18 17:19:06 +05304 */
5
6#include <common.h>
7#include <command.h>
Simon Glass7b51b572019-08-01 09:46:52 -06008#include <env.h>
Zhao Qiangd4683772015-08-28 10:31:50 +08009#include <hwconfig.h>
Priyanka Jain062ef1a2013-10-18 17:19:06 +053010#include <netdev.h>
11#include <linux/compiler.h>
12#include <asm/mmu.h>
13#include <asm/processor.h>
14#include <asm/cache.h>
15#include <asm/immap_85xx.h>
Zhao Qiangd4683772015-08-28 10:31:50 +080016#include <asm/fsl_fdt.h>
Priyanka Jain062ef1a2013-10-18 17:19:06 +053017#include <asm/fsl_law.h>
18#include <asm/fsl_serdes.h>
Priyanka Jain062ef1a2013-10-18 17:19:06 +053019#include <asm/fsl_liodn.h>
20#include <fm_eth.h>
Tang Yuantian00233522014-11-21 11:17:16 +080021#include "../common/sleep.h"
Priyanka Jain062ef1a2013-10-18 17:19:06 +053022#include "t104xrdb.h"
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +053023#include "cpld.h"
Priyanka Jain062ef1a2013-10-18 17:19:06 +053024
25DECLARE_GLOBAL_DATA_PTR;
26
27int checkboard(void)
28{
29 struct cpu_type *cpu = gd->arch.cpu;
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +053030 u8 sw;
Priyanka Jain062ef1a2013-10-18 17:19:06 +053031
York Sun78e56992016-11-21 11:25:26 -080032#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
Priyanka Jain4b6067a2015-06-05 15:29:02 +053033 printf("Board: %sD4RDB\n", cpu->name);
34#else
Priyanka Jain062ef1a2013-10-18 17:19:06 +053035 printf("Board: %sRDB\n", cpu->name);
Priyanka Jain4b6067a2015-06-05 15:29:02 +053036#endif
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +053037 printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
38 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
39
40 sw = CPLD_READ(flash_ctl_status);
41 sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
42
Priyanka Jainf2af1c32015-07-30 10:20:18 +053043 printf("vBank: %d\n", sw);
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +053044
Priyanka Jain062ef1a2013-10-18 17:19:06 +053045 return 0;
46}
47
Tang Yuantian00233522014-11-21 11:17:16 +080048int board_early_init_f(void)
49{
50#if defined(CONFIG_DEEP_SLEEP)
51 if (is_warm_boot())
52 fsl_dp_disable_console();
53#endif
54
55 return 0;
56}
57
Priyanka Jain062ef1a2013-10-18 17:19:06 +053058int board_early_init_r(void)
59{
60#ifdef CONFIG_SYS_FLASH_BASE
61 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun9d045682014-06-24 21:16:20 -070062 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Priyanka Jain062ef1a2013-10-18 17:19:06 +053063
64 /*
65 * Remap Boot flash region to caching-inhibited
66 * so that flash can be erased properly.
67 */
68
69 /* Flush d-cache and invalidate i-cache of any FLASH data */
70 flush_dcache();
71 invalidate_icache();
72
York Sun9d045682014-06-24 21:16:20 -070073 if (flash_esel == -1) {
74 /* very unlikely unless something is messed up */
75 puts("Error: Could not find TLB for FLASH BASE\n");
76 flash_esel = 2; /* give our best effort to continue */
77 } else {
78 /* invalidate existing TLB entry for flash */
79 disable_tlb(flash_esel);
80 }
Priyanka Jain062ef1a2013-10-18 17:19:06 +053081
82 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
83 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
84 0, flash_esel, BOOKE_PAGESZ_256M, 1);
85#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +053086 return 0;
87}
88
89int misc_init_r(void)
90{
Priyanka Jain4b6067a2015-06-05 15:29:02 +053091 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
92 u32 srds_s1;
93
94 srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
95
96 printf("SERDES Reference : 0x%X\n", srds_s1);
97
98 /* select SGMII*/
99 if (srds_s1 == 0x86)
100 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
101 MISC_CTL_SG_SEL);
102
103 /* select SGMII and Aurora*/
104 if (srds_s1 == 0x8E)
105 CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
106 MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
107
York Suna0167352016-11-21 10:46:53 -0800108#if defined(CONFIG_TARGET_T1040D4RDB)
Zhao Qiangd4683772015-08-28 10:31:50 +0800109 if (hwconfig("qe-tdm")) {
110 CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
111 MISC_MUX_QE_TDM);
112 printf("QECSR : 0x%02x, mux to qe-tdm\n",
113 CPLD_READ(sfp_ctl_status));
114 }
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530115 /* Mask all CPLD interrupt sources, except QSGMII interrupts */
116 if (CPLD_READ(sw_ver) < 0x03) {
117 debug("CPLD SW version 0x%02x doesn't support int_mask\n",
118 CPLD_READ(sw_ver));
119 } else {
120 CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
121 ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
122 }
123#endif
124
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530125 return 0;
126}
127
Simon Glasse895a4b2014-10-23 18:58:47 -0600128int ft_board_setup(void *blob, bd_t *bd)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530129{
130 phys_addr_t base;
131 phys_size_t size;
132
133 ft_cpu_setup(blob, bd);
134
Simon Glass723806c2017-08-03 12:22:15 -0600135 base = env_get_bootm_low();
136 size = env_get_bootm_size();
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530137
138 fdt_fixup_memory(blob, (u64)base, (u64)size);
139
140#ifdef CONFIG_PCI
141 pci_of_setup(blob, bd);
142#endif
143
144 fdt_fixup_liodn(blob);
145
146#ifdef CONFIG_HAS_FSL_DR_USB
Sriram Dasha5c289b2016-09-16 17:12:15 +0530147 fsl_fdt_fixup_dr_usb(blob, bd);
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530148#endif
149
150#ifdef CONFIG_SYS_DPAA_FMAN
151 fdt_fixup_fman_ethernet(blob);
152#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600153
Zhao Qiangd4683772015-08-28 10:31:50 +0800154 if (hwconfig("qe-tdm"))
155 fdt_del_diu(blob);
Simon Glasse895a4b2014-10-23 18:58:47 -0600156 return 0;
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530157}