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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 224beb833e544b802f08765271cec07667d39669 / . / board / csb272 / init.S
blob: bf1d98680d1226b0c1cc959cf80c8be3713453fa [file] [log] [blame]
Wolfgang Denk46263f22013-07-28 22:12:45 +0200[diff] [blame]1/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +0200[diff] [blame]2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +0200[diff] [blame]3 */
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]4#include <config.h>
Stefan Roeseb36df562010-09-09 19:18:00 +0200[diff] [blame]5#include <asm/ppc4xx.h>
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]6
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]7#include <ppc_asm.tmpl>
8#include <ppc_defs.h>
9
10#include <asm/cache.h>
11#include <asm/mmu.h>
12
13#define LI32(reg,val) \
14 addis reg,0,val@h;\
15 ori reg,reg,val@l
16
17#define WDCR_EBC(reg,val) \
18 addi r4,0,reg;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]19 mtdcr EBC0_CFGADDR,r4;\
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]20 addis r4,0,val@h;\
21 ori r4,r4,val@l;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]22 mtdcr EBC0_CFGDATA,r4
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]23
24#define WDCR_SDRAM(reg,val) \
25 addi r4,0,reg;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]26 mtdcr SDRAM0_CFGADDR,r4;\
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]27 addis r4,0,val@h;\
28 ori r4,r4,val@l;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]29 mtdcr SDRAM0_CFGDATA,r4
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]30
31/******************************************************************************
32 * Function: ext_bus_cntlr_init
33 *
34 * Description: Configures EBC Controller and a few basic chip selects.
35 *
36 * CS0 is setup to get the Boot Flash out of the addresss range
37 * so that we may setup a stack. CS7 is setup so that we can
38 * access and reset the hardware watchdog.
39 *
40 * IMPORTANT: For pass1 this code must run from
41 * cache since you can not reliably change a peripheral banks
42 * timing register (pbxap) while running code from that bank.
43 * For ex., since we are running from ROM on bank 0, we can NOT
44 * execute the code that modifies bank 0 timings from ROM, so
45 * we run it from cache.
46 *
47 * Notes: Does NOT use the stack.
48 *****************************************************************************/
49 .section ".text"
50 .align 2
51 .globl ext_bus_cntlr_init
52 .type ext_bus_cntlr_init, @function
53ext_bus_cntlr_init:
54 mflr r0
55 /********************************************************************
56 * Prefetch entire ext_bus_cntrl_init function into the icache.
57 * This is necessary because we are going to change the same CS we
58 * are executing from. Otherwise a CPU lockup may occur.
59 *******************************************************************/
60 bl ..getAddr
61..getAddr:
62 mflr r3 /* get address of ..getAddr */
63
64 /* Calculate number of cache lines for this function */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]65 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]66 mtctr r4
67..ebcloop:
68 icbt r0, r3 /* prefetch cache line for addr in r3*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]69 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]70 bdnz ..ebcloop /* continue for $CTR cache lines */
71
72 /********************************************************************
73 * Delay to ensure all accesses to ROM are complete before changing
74 * bank 0 timings. 200usec should be enough.
75 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
76 *******************************************************************/
77 addis r3, 0, 0x0
78 ori r3, r3, 0xA000 /* wait 200us from reset */
79 mtctr r3
80..spinlp:
81 bdnz ..spinlp /* spin loop */
82
83 /********************************************************************
84 * SETUP CPC0_CR0
85 *******************************************************************/
86 LI32(r4, 0x007000c0)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]87 mtdcr CPC0_CR0, r4
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]88
89 /********************************************************************
90 * Setup CPC0_CR1: Change PCIINT signal to PerWE
91 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]92 mfdcr r4, CPC0_CR1
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]93 ori r4, r4, 0x4000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]94 mtdcr CPC0_CR1, r4
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]95
96 /********************************************************************
97 * Setup External Bus Controller (EBC).
98 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]99 WDCR_EBC(EBC0_CFG, 0xd84c0000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]100 /********************************************************************
101 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
102 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]103 /*WDCR_EBC(PB1AP, 0x02869200)*/
104 WDCR_EBC(PB1AP, 0x07869200)
105 WDCR_EBC(PB0CR, 0xfe0bc000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]106 /********************************************************************
107 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
108 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]109 WDCR_EBC(PB1AP, 0x1f869200)
110 WDCR_EBC(PB1CR, 0xf0818000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]111 /********************************************************************
112 * Memory Bank 2 (Epson S1D13506) initialization
113 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]114 WDCR_EBC(PB2AP, 0x05860300)
115 WDCR_EBC(PB2CR, 0xf045a000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]116 /********************************************************************
117 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
118 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]119 WDCR_EBC(PB3AP, 0x0387d200)
120 WDCR_EBC(PB3CR, 0xf021c000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]121 /********************************************************************
122 * Memory Bank 4-7 (Unused) initialization
123 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]124 WDCR_EBC(PB4AP, 0)
125 WDCR_EBC(PB4CR, 0)
126 WDCR_EBC(PB5AP, 0)
127 WDCR_EBC(PB5CR, 0)
128 WDCR_EBC(PB6AP, 0)
129 WDCR_EBC(PB6CR, 0)
130 WDCR_EBC(PB7AP, 0)
131 WDCR_EBC(PB7CR, 0)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]132
133 /* We are all done */
134 mtlr r0 /* Restore link register */
135 blr /* Return to calling function */
136.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
137/* end ext_bus_cntlr_init() */
138
139/******************************************************************************
140 * Function: sdram_init
141 *
142 * Description: Configures SDRAM memory banks.
143 *
144 * Notes: Does NOT use the stack.
145 *****************************************************************************/
146 .section ".text"
147 .align 2
148 .globl sdram_init
149 .type sdram_init, @function
150sdram_init:
151
152 /*
153 * Disable memory controller to allow
154 * values to be changed.
155 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]156 WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]157
158 /*
159 * Configure Memory Banks
160 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]161 WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
162 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
163 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
164 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]165
166 /*
167 * Set up SDTR1 (SDRAM Timing Register)
168 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]169 WDCR_SDRAM(SDRAM0_TR, 0x00854009)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]170
171 /*
172 * Set RTR (Refresh Timing Register)
173 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]174 WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
175 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]176
177 /********************************************************************
178 * Delay to ensure 200usec have elapsed since reset. Assume worst
179 * case that the core is running 200Mhz:
180 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
181 *******************************************************************/
182 addis r3, 0, 0x0000
183 ori r3, r3, 0xA000 /* Wait >200us from reset */
184 mtctr r3
185..spinlp2:
186 bdnz ..spinlp2 /* spin loop */
187
188 /********************************************************************
189 * Set memory controller options reg, MCOPT1.
190 *******************************************************************/
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]191 WDCR_SDRAM(SDRAM0_CFG,0x80800000)
wdenkcd0a9de2004-02-23 20:48:38 +0000[diff] [blame]192
193..sdri_done:
194 blr /* Return to calling function */
195.Lfe1: .size sdram_init,.Lfe1-sdram_init
196/* end sdram_init() */