| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_RK3128_COMMON_H |
| 7 | #define __CONFIG_RK3128_COMMON_H |
| 8 | |
| 9 | #include "rockchip-common.h" |
| 10 | |
| Tom Rini | 65cc0e2 | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 11 | #define CFG_SYS_HZ_CLOCK 24000000 |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 12 | |
| Tom Rini | 7b5f75c | 2022-12-04 10:04:13 -0500 | [diff] [blame] | 13 | #define CFG_IRAM_BASE 0x10080000 |
| Kever Yang | 5f24680 | 2019-07-22 19:59:09 +0800 | [diff] [blame] | 14 | |
| Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 15 | #define CFG_SYS_SDRAM_BASE 0x60000000 |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 16 | #define SDRAM_MAX_SIZE 0x80000000 |
| 17 | |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 18 | #define ENV_MEM_LAYOUT_SETTINGS \ |
| 19 | "scriptaddr=0x60500000\0" \ |
| 20 | "pxefile_addr_r=0x60600000\0" \ |
| 21 | "fdt_addr_r=0x61f00000\0" \ |
| 22 | "kernel_addr_r=0x62000000\0" \ |
| 23 | "ramdisk_addr_r=0x64000000\0" |
| 24 | |
| Tom Rini | 0613c36 | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 25 | #define CFG_EXTRA_ENV_SETTINGS \ |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 26 | ENV_MEM_LAYOUT_SETTINGS \ |
| Klaus Goger | a2a5053 | 2018-05-25 23:45:05 +0200 | [diff] [blame] | 27 | "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 28 | "partitions=" PARTS_DEFAULT \ |
| Simon Glass | 7755dc5 | 2023-04-24 13:49:51 +1200 | [diff] [blame] | 29 | "boot_targets=" BOOT_TARGETS "\0" |
| Kever Yang | daeed1d | 2017-11-28 16:04:16 +0800 | [diff] [blame] | 30 | |
| 31 | #endif |