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wdenk7c202ac2002-09-09 08:35:37 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Alex Zuepke <azu@sysgo.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26
27/* ------------------------------------------------------------------------- */
28
29
30/*
31 * Miscelaneous platform dependent initialisations
32 */
33
34int board_init (void)
35{
36 DECLARE_GLOBAL_DATA_PTR;
37
38 /* memory and cpu-speed are setup before relocation */
39 /* but if we use InfernoLoader, we must do some inits here */
40
41#ifdef CONFIG_INFERNO
42 {
43 unsigned long temp;
44 __asm__ __volatile__(/* disable MMU, enable icache */
45 "mrc p15, 0, %0, c1, c0\n"
46 "bic %0, %0, #0x00002000\n"
47 "bic %0, %0, #0x0000000f\n"
48 "orr %0, %0, #0x00001000\n"
49 "orr %0, %0, #0x00000002\n"
50 "mcr p15, 0, %0, c1, c0\n"
51 /* flush caches */
52 "mov %0, #0\n"
53 "mcr p15, 0, %0, c7, c7, 0\n"
54 "mcr p15, 0, %0, c8, c7, 0\n"
55 : "=r" (temp)
56 :
57 : "memory");
58 /* setup PCMCIA timing */
59 temp = 0xa0000018;
60 *(unsigned long *)temp = 0x00060006;
61
62 }
63#endif /* CONFIG_INIT_CRITICAL */
64
65 /* arch number for shannon */
66 gd->bd->bi_arch_number = 97;
67
68 /* adress of boot parameters */
69 gd->bd->bi_boot_params = 0xc0000100;
70
71 return 0;
72}
73
74int dram_init (void)
75{
76#if defined(PHYS_SDRAM_1) || defined(PHYS_SDRAM_2) || \
77 defined(PHYS_SDRAM_3) || defined(PHYS_SDRAM_4)
78 DECLARE_GLOBAL_DATA_PTR;
79 bd_t *bd = gd->bd;
80#endif
81
82#ifdef PHYS_SDRAM_1
83 bd->bi_dram[0].start = PHYS_SDRAM_1;
84 bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
85#endif
86
87#ifdef PHYS_SDRAM_2
88 bd->bi_dram[1].start = PHYS_SDRAM_2;
89 bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
90#endif
91
92#ifdef PHYS_SDRAM_3
93 bd->bi_dram[2].start = PHYS_SDRAM_3;
94 bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
95#endif
96
97#ifdef PHYS_SDRAM_4
98 bd->bi_dram[3].start = PHYS_SDRAM_4;
99 bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
100#endif
101
102 return (0);
103}