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Jon Loeliger0cde4b02007-04-11 16:50:57 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
Jon Loeliger0cde4b02007-04-11 16:50:57 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeliger0cde4b02007-04-11 16:50:57 -05005 */
6
7/*
8 * mpc8544ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun9ae14ca2015-08-18 12:35:52 -070014#define CONFIG_DISPLAY_BOARDINFO
15
Jon Loeliger0cde4b02007-04-11 16:50:57 -050016/* High Level Configuration Options */
17#define CONFIG_BOOKE 1 /* BOOKE */
18#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050019#define CONFIG_MPC8544 1
20#define CONFIG_MPC8544DS 1
21
Wolfgang Denk2ae18242010-10-06 09:05:45 +020022#ifndef CONFIG_SYS_TEXT_BASE
23#define CONFIG_SYS_TEXT_BASE 0xfff80000
24#endif
25
Ed Swarthout837f1ba2007-07-27 01:50:51 -050026#define CONFIG_PCI 1 /* Enable PCI/PCIE */
27#define CONFIG_PCI1 1 /* PCI controller 1 */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040028#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
29#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
30#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
Ed Swarthout837f1ba2007-07-27 01:50:51 -050031#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000032#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala8ff3de62007-12-07 12:17:34 -060033#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050034#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050035
Kumar Gala4bcae9c2008-01-16 01:16:16 -060036#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
37
Ed Swarthout837f1ba2007-07-27 01:50:51 -050038#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050039#define CONFIG_ENV_OVERWRITE
Ed Swarthout837f1ba2007-07-27 01:50:51 -050040#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050041
Jon Loeliger0cde4b02007-04-11 16:50:57 -050042#ifndef __ASSEMBLY__
43extern unsigned long get_board_sys_clk(unsigned long dummy);
44#endif
45#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
46
47/*
48 * These can be toggled for performance analysis, otherwise use default.
49 */
Ed Swarthout837f1ba2007-07-27 01:50:51 -050050#define CONFIG_L2_CACHE /* toggle L2 cache */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050051#define CONFIG_BTB /* toggle branch predition */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050052
53/*
54 * Only possible on E500 Version 2 or newer cores.
55 */
56#define CONFIG_ENABLE_36BIT_PHYS 1
57
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59#define CONFIG_SYS_MEMTEST_END 0x00400000
Ed Swarthout837f1ba2007-07-27 01:50:51 -050060#define CONFIG_PANIC_HANG /* do not reset board on panic */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050061
Timur Tabie46fedf2011-08-04 18:03:41 -050062#define CONFIG_SYS_CCSRBAR 0xe0000000
63#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeliger0cde4b02007-04-11 16:50:57 -050064
Kumar Gala1167a2f2008-08-26 08:02:30 -050065/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070066#define CONFIG_SYS_FSL_DDR2
Kumar Gala1167a2f2008-08-26 08:02:30 -050067#undef CONFIG_FSL_DDR_INTERACTIVE
68#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
69#define CONFIG_DDR_SPD
Jon Loeliger0cde4b02007-04-11 16:50:57 -050070
Dave Liu9b0ad1b2008-10-28 17:53:38 +080071#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala1167a2f2008-08-26 08:02:30 -050072#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
75#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala1167a2f2008-08-26 08:02:30 -050076#define CONFIG_VERY_BIG_RAM
77
78#define CONFIG_NUM_DDR_CONTROLLERS 1
79#define CONFIG_DIMM_SLOTS_PER_CTLR 1
80#define CONFIG_CHIP_SELECTS_PER_CTRL 2
81
82/* I2C addresses of SPD EEPROMs */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050083#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
84
Kumar Gala1167a2f2008-08-26 08:02:30 -050085/* Make sure required options are set */
Jon Loeliger0cde4b02007-04-11 16:50:57 -050086#ifndef CONFIG_SPD_EEPROM
87#error ("CONFIG_SPD_EEPROM is required")
88#endif
89
90#undef CONFIG_CLOCKS_IN_MHZ
91
92/*
93 * Memory map
94 *
95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
96 *
97 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
98 *
99 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
100 *
101 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
102 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
103 *
104 * Localbus cacheable
105 *
106 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
107 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
108 *
109 * Localbus non-cacheable
110 *
111 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
112 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
113 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
114 *
115 */
116
117/*
118 * Local Bus Definitions
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_BR0_PRELIM 0xff801001
125#define CONFIG_SYS_BR1_PRELIM 0xfe801001
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_OR0_PRELIM 0xff806e65
128#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_FLASH_QUIET_TEST
133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
134#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
135#undef CONFIG_SYS_FLASH_CHECKSUM
136#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala81e56e92008-06-09 18:55:38 -0500138#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500139
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200140#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500141
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200142#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_CFI
144#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
149#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
152#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500153
Kim Phillips7608d752007-08-21 17:00:17 -0500154#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500155#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
156#define PIXIS_ID 0x0 /* Board ID at offset 0 */
157#define PIXIS_VER 0x1 /* Board version at offset 1 */
158#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
159#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
160#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
161 * register */
162#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
163#define PIXIS_VCTL 0x10 /* VELA Control Register */
164#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
165#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
166#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500167#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
168#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500169#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
170#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
171#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
172#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Andy Fleming5a8a1632008-08-31 16:33:30 -0500173#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Andy Fleming5a8a1632008-08-31 16:33:30 -0500175#define PIXIS_VSPEED2_TSEC1SER 0x2
176#define PIXIS_VSPEED2_TSEC3SER 0x1
177#define PIXIS_VCFGEN1_TSEC1SER 0x20
178#define PIXIS_VCFGEN1_TSEC3SER 0x40
Liu Yubff188b2008-10-10 11:40:58 +0800179#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
180#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_LOCK 1
183#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200184#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500185
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200186#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
190#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500191
192/* Serial Port - controlled on board with jumper J8
193 * open - index 2
194 * shorted - index 1
195 */
196#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_NS16550_SERIAL
198#define CONFIG_SYS_NS16550_REG_SIZE 1
199#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500202 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
205#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500206
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500207/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200208#define CONFIG_SYS_I2C
209#define CONFIG_SYS_I2C_FSL
210#define CONFIG_SYS_FSL_I2C_SPEED 400000
211#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
212#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
213#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500215
216/*
217 * General PCI
218 * Memory space is mapped 1-1, but I/O space must start from 0.
219 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600220#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600222#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500224
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600225#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600226#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600227#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600229#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600230#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
232#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500233
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500234/* controller 2, Slot 1, tgtid 1, Base address 9000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600235#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600236#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600237#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600238#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600240#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600241#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
243#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500244
245/* controller 1, Slot 2,tgtid 2, Base address a000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600246#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600247#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600248#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600249#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600251#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600252#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
254#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500255
256/* controller 3, direct to uli, tgtid 3, Base address b000 */
Kumar Gala64a16862010-12-17 06:01:24 -0600257#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600258#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600259#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600260#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600262#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
Kumar Gala5f91ef62008-12-02 16:08:37 -0600263#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
265#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600266#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
Kumar Gala10795f42008-12-02 16:08:36 -0600267#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600268#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500270
271#if defined(CONFIG_PCI)
272
Kumar Gala630d9bf2008-07-14 14:07:03 -0500273/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600274#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Kumar Gala630d9bf2008-07-14 14:07:03 -0500275
276/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600277/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala630d9bf2008-07-14 14:07:03 -0500278
279/* video */
280#define CONFIG_VIDEO
281
282#if defined(CONFIG_VIDEO)
283#define CONFIG_BIOSEMU
284#define CONFIG_CFB_CONSOLE
285#define CONFIG_VIDEO_SW_CURSOR
286#define CONFIG_VGA_AS_SINGLE_DEVICE
287#define CONFIG_ATI_RADEON_FB
288#define CONFIG_VIDEO_LOGO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala630d9bf2008-07-14 14:07:03 -0500290#endif
291
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500292#define CONFIG_PCI_PNP /* do pci plug-and-play */
293
294#undef CONFIG_EEPRO100
295#undef CONFIG_TULIP
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500296
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500297#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600298 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
299 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500300 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
301#endif
302
303#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
304#define CONFIG_DOS_PARTITION
305#define CONFIG_SCSI_AHCI
306
307#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500308#define CONFIG_LIBATA
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500309#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
311#define CONFIG_SYS_SCSI_MAX_LUN 1
312#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
313#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500314#endif /* SCSCI */
315
316#endif /* CONFIG_PCI */
317
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500318#if defined(CONFIG_TSEC_ENET)
319
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500320#define CONFIG_MII 1 /* MII PHY management */
321#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
Kim Phillips255a35772007-05-16 16:52:19 -0500322#define CONFIG_TSEC1 1
323#define CONFIG_TSEC1_NAME "eTSEC1"
324#define CONFIG_TSEC3 1
325#define CONFIG_TSEC3_NAME "eTSEC3"
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500326
Liu Yubff188b2008-10-10 11:40:58 +0800327#define CONFIG_PIXIS_SGMII_CMD
Andy Fleming652f7c22008-08-31 16:33:28 -0500328#define CONFIG_FSL_SGMII_RISER 1
329#define SGMII_RISER_PHY_OFFSET 0x1c
330
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500331#define TSEC1_PHY_ADDR 0
332#define TSEC3_PHY_ADDR 1
333
Andy Fleming3a790132007-08-15 20:03:25 -0500334#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
335#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
336
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500337#define TSEC1_PHYIDX 0
338#define TSEC3_PHYIDX 0
339
340#define CONFIG_ETHPRIME "eTSEC1"
341
342#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500343#endif /* CONFIG_TSEC_ENET */
344
345/*
346 * Environment
347 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200348#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200350#define CONFIG_ENV_ADDR 0xfff80000
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500351#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500353#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200354#define CONFIG_ENV_SIZE 0x2000
355#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500356
357#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500359
Jon Loeliger2835e512007-06-13 13:22:08 -0500360/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500361 * BOOTP options
362 */
363#define CONFIG_BOOTP_BOOTFILESIZE
364#define CONFIG_BOOTP_BOOTPATH
365#define CONFIG_BOOTP_GATEWAY
366#define CONFIG_BOOTP_HOSTNAME
367
Jon Loeliger659e2f62007-07-10 09:10:49 -0500368/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500369 * Command line configuration.
370 */
Kumar Gala1c9aa762008-09-22 23:40:42 -0500371#define CONFIG_CMD_IRQ
Becky Bruce199e2622010-06-17 11:37:25 -0500372#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500373
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500374#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500375 #define CONFIG_CMD_PCI
Simon Glassc649e3c2016-05-01 11:36:02 -0600376 #define CONFIG_SCSI
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500377#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500378
Hongtao Jia86a194b2012-12-20 19:39:53 +0000379/*
380 * USB
381 */
382#define CONFIG_USB_EHCI
383
384#ifdef CONFIG_USB_EHCI
Hongtao Jia86a194b2012-12-20 19:39:53 +0000385#define CONFIG_USB_EHCI_PCI
386#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
387#define CONFIG_USB_STORAGE
388#define CONFIG_PCI_EHCI_DEVICE 0
389#endif
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500390
391#undef CONFIG_WATCHDOG /* watchdog disabled */
392
393/*
394 * Miscellaneous configurable options
395 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500397#define CONFIG_CMDLINE_EDITING /* Command-line editing */
398#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger2835e512007-06-13 13:22:08 -0500400#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500402#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500404#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
406#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
407#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500408
409/*
410 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500411 * have to be in the first 64 MB of memory, since this is
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500412 * the maximum mapped by the Linux kernel during initialization.
413 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500414#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
415#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500416
Jon Loeliger2835e512007-06-13 13:22:08 -0500417#if defined(CONFIG_CMD_KGDB)
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500418#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500419#endif
420
421/*
422 * Environment Configuration
423 */
424
425/* The mac addresses for all ethernet interface */
426#if defined(CONFIG_TSEC_ENET)
Kumar Galaea5877e2007-08-16 11:01:21 -0500427#define CONFIG_HAS_ETH0
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500428#define CONFIG_HAS_ETH1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500429#endif
430
431#define CONFIG_IPADDR 192.168.1.251
432
433#define CONFIG_HOSTNAME 8544ds_unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000434#define CONFIG_ROOTPATH "/nfs/mpc85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000435#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500436#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500437
Kumar Gala50c03c82007-11-27 22:42:34 -0600438#define CONFIG_SERVERIP 192.168.1.1
439#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500440#define CONFIG_NETMASK 255.255.0.0
441
442#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
443
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500444#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500445
446#define CONFIG_BAUDRATE 115200
447
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500448#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200449"netdev=eth0\0" \
450"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
451"tftpflash=tftpboot $loadaddr $uboot; " \
452 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
453 " +$filesize; " \
454 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
455 " +$filesize; " \
456 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
457 " $filesize; " \
458 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
459 " +$filesize; " \
460 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
461 " $filesize\0" \
462"consoledev=ttyS0\0" \
463"ramdiskaddr=2000000\0" \
464"ramdiskfile=8544ds/ramdisk.uboot\0" \
465"fdtaddr=c00000\0" \
466"fdtfile=8544ds/mpc8544ds.dtb\0" \
467"bdev=sda3\0"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500468
469#define CONFIG_NFSBOOTCOMMAND \
470 "setenv bootargs root=/dev/nfs rw " \
471 "nfsroot=$serverip:$rootpath " \
472 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
473 "console=$consoledev,$baudrate $othbootargs;" \
474 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600475 "tftp $fdtaddr $fdtfile;" \
476 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500477
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500478#define CONFIG_RAMBOOTCOMMAND \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500479 "setenv bootargs root=/dev/ram rw " \
480 "console=$consoledev,$baudrate $othbootargs;" \
481 "tftp $ramdiskaddr $ramdiskfile;" \
482 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600483 "tftp $fdtaddr $fdtfile;" \
484 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500485
Ed Swarthout837f1ba2007-07-27 01:50:51 -0500486#define CONFIG_BOOTCOMMAND \
487 "setenv bootargs root=/dev/$bdev rw " \
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500488 "console=$consoledev,$baudrate $othbootargs;" \
489 "tftp $loadaddr $bootfile;" \
Kumar Gala50c03c82007-11-27 22:42:34 -0600490 "tftp $fdtaddr $fdtfile;" \
491 "bootm $loadaddr - $fdtaddr"
Jon Loeliger0cde4b02007-04-11 16:50:57 -0500492
493#endif /* __CONFIG_H */