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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkc837dcb2004-01-20 23:12:12 +000015 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk0f8c9762002-08-19 11:57:05 +000016 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
wdenk0f8c9762002-08-19 11:57:05 +000038
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenk0f8c9762002-08-19 11:57:05 +000040
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
wdenk0f8c9762002-08-19 11:57:05 +000042
wdenkc837dcb2004-01-20 23:12:12 +000043#define CONFIG_CPUCLOCK 66
44#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
wdenk0f8c9762002-08-19 11:57:05 +000045
wdenkc837dcb2004-01-20 23:12:12 +000046#define CONFIG_BAUDRATE 9600
wdenk0f8c9762002-08-19 11:57:05 +000047#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
48#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */
49
wdenkc837dcb2004-01-20 23:12:12 +000050#undef CONFIG_BOOTARGS
wdenk0f8c9762002-08-19 11:57:05 +000051
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +000054
55#undef CONFIG_WATCHDOG /* watchdog disabled */
56
57#define CONFIG_IPADDR 10.0.18.222
58#define CONFIG_SERVERIP 10.0.18.190
59
Jon Loeliger3c3227f2007-07-07 20:40:43 -050060
61/*
Jon Loeliger11799432007-07-10 09:02:57 -050062 * BOOTP options
63 */
64#define CONFIG_BOOTP_BOOTFILESIZE
65#define CONFIG_BOOTP_BOOTPATH
66#define CONFIG_BOOTP_GATEWAY
67#define CONFIG_BOOTP_HOSTNAME
68
69
70/*
Jon Loeliger3c3227f2007-07-07 20:40:43 -050071 * Command line configuration.
72 */
73#include <config_cmd_default.h>
74
75#define CONFIG_CMD_BSP
76
wdenk0f8c9762002-08-19 11:57:05 +000077
78#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
79#define CONFIG_SOFT_I2C /* Software I2C support enabled */
80#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenk0f8c9762002-08-19 11:57:05 +000082
wdenk0f8c9762002-08-19 11:57:05 +000083/*
84 * Miscellaneous configurable options
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_LONGHELP /* undef to save memory */
87#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger3c3227f2007-07-07 20:40:43 -050088#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000090#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000092#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
94#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
95#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +000096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk0f8c9762002-08-19 11:57:05 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
100#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000101
102/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000104 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000109
110#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
111
112/*-----------------------------------------------------------------------
113 * Definitions for initial stack pointer and data area (in DPRAM)
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
116#define CONFIG_SYS_INIT_RAM_END 0x0f00 /* End of used area in RAM */
117#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
118#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
119#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000120
121/*-----------------------------------------------------------------------
122 * Start addresses for the final memory configuration
123 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000125 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_SDRAM_BASE 0x00000000
127#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
128#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
129#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 128 kB for Monitor */
130#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk0f8c9762002-08-19 11:57:05 +0000131
132/*
133 * For booting Linux, the board info and command line data
134 * have to be in the first 8 MB of memory, since this is
135 * the maximum mapped by the Linux kernel during initialization.
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000138/*-----------------------------------------------------------------------
139 * FLASH organization
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
142#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
145#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
148#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
149#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
wdenk0f8c9762002-08-19 11:57:05 +0000150/*
151 * The following defines are added for buggy IOP480 byte interface.
152 * All other boards should use the standard values (CPCI405 etc.)
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */
155#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */
156#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */
wdenk0f8c9762002-08-19 11:57:05 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk0f8c9762002-08-19 11:57:05 +0000159
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200160#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200161#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
162#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
wdenk0f8c9762002-08-19 11:57:05 +0000163
164#if 0
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200165#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
wdenk0f8c9762002-08-19 11:57:05 +0000166#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200167#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
wdenk0f8c9762002-08-19 11:57:05 +0000168#endif
169
170/*-----------------------------------------------------------------------
171 * PCI stuff
172 */
173#define CONFIG_PCI /* include pci support */
174#undef CONFIG_PCI_PNP
175
wdenkc837dcb2004-01-20 23:12:12 +0000176#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenk0f8c9762002-08-19 11:57:05 +0000177
178#define CONFIG_TULIP
179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_ETH_DEV_FN 0x0000
181#define CONFIG_SYS_ETH_IOBASE 0x0fff0000
182#define CONFIG_SYS_PCI9054_DEV_FN 0x0800
183#define CONFIG_SYS_PCI9054_IOBASE 0x0eff0000
wdenk0f8c9762002-08-19 11:57:05 +0000184
wdenk0f8c9762002-08-19 11:57:05 +0000185/*
186 * Init Memory Controller:
187 *
188 * BR0/1 and OR0/1 (FLASH)
189 */
190
191#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
192
193
194/*
195 * Internal Definitions
196 *
197 * Boot Flags
198 */
199#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
200#define BOOTFLAG_WARM 0x02 /* Software reboot */
201
202#endif /* __CONFIG_H */