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wdenk03f5c552004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8555cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
wdenk03f5c552004-10-10 21:21:55 +000029#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050036#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000037#define CONFIG_MPC8555 1 /* MPC8555 specific */
38#define CONFIG_MPC8555CDS 1 /* MPC8555CDS board specific */
39
40#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050041#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000043#define CONFIG_ENV_OVERWRITE
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060044#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk03f5c552004-10-10 21:21:55 +000045
Jon Loeliger25eedb22008-03-19 15:02:07 -050046#define CONFIG_FSL_VIA
Timur Tabie8d18542008-07-18 16:52:23 +020047
Jon Loeliger25eedb22008-03-19 15:02:07 -050048
wdenk03f5c552004-10-10 21:21:55 +000049/*
50 * When initializing flash, if we cannot find the manufacturer ID,
51 * assume this is the AMD flash associated with the CDS board.
52 * This allows booting from a promjet.
53 */
54#define CONFIG_ASSUME_AMD_FLASH
55
wdenk03f5c552004-10-10 21:21:55 +000056#ifndef __ASSEMBLY__
57extern unsigned long get_clock_freq(void);
58#endif
59#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
60
61/*
62 * These can be toggled for performance analysis, otherwise use default.
63 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020064#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000065#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
68#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000069
wdenk03f5c552004-10-10 21:21:55 +000070/*
71 * Base addresses -- Note these are effective addresses where the
72 * actual resources get mapped (not physical addresses)
73 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
75#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
76#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
77#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk03f5c552004-10-10 21:21:55 +000078
Jon Loeliger2b40edb2008-03-18 11:12:42 -050079/* DDR Setup */
80#define CONFIG_FSL_DDR1
81#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
82#define CONFIG_DDR_SPD
83#undef CONFIG_FSL_DDR_INTERACTIVE
84
85#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
88#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000089
Jon Loeliger2b40edb2008-03-18 11:12:42 -050090#define CONFIG_NUM_DDR_CONTROLLERS 1
91#define CONFIG_DIMM_SLOTS_PER_CTLR 1
92#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk03f5c552004-10-10 21:21:55 +000093
Jon Loeliger2b40edb2008-03-18 11:12:42 -050094/* I2C addresses of SPD EEPROMs */
95#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
96
97/* Make sure required options are set */
wdenk03f5c552004-10-10 21:21:55 +000098#ifndef CONFIG_SPD_EEPROM
99#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
100#endif
101
Jon Loeliger7202d432005-07-25 11:13:26 -0500102#undef CONFIG_CLOCKS_IN_MHZ
103
wdenk03f5c552004-10-10 21:21:55 +0000104/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500105 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +0000106 */
Jon Loeliger7202d432005-07-25 11:13:26 -0500107
108/*
109 * FLASH on the Local Bus
110 * Two banks, 8M each, using the CFI driver.
111 * Boot from BR0/OR0 bank at 0xff00_0000
112 * Alternate BR1/OR1 bank at 0xff80_0000
113 *
114 * BR0, BR1:
115 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
116 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
117 * Port Size = 16 bits = BRx[19:20] = 10
118 * Use GPCM = BRx[24:26] = 000
119 * Valid = BRx[31] = 1
120 *
121 * 0 4 8 12 16 20 24 28
122 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
123 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
124 *
125 * OR0, OR1:
126 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
127 * Reserved ORx[17:18] = 11, confusion here?
128 * CSNT = ORx[20] = 1
129 * ACS = half cycle delay = ORx[21:22] = 11
130 * SCY = 6 = ORx[24:27] = 0110
131 * TRLX = use relaxed timing = ORx[29] = 1
132 * EAD = use external address latch delay = OR[31] = 1
133 *
134 * 0 4 8 12 16 20 24 28
135 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
136 */
137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_BR0_PRELIM 0xff801001
141#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_OR0_PRELIM 0xff806e65
144#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
147#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
148#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
149#undef CONFIG_SYS_FLASH_CHECKSUM
150#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
151#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000154
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200155#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_CFI
157#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000158
wdenk03f5c552004-10-10 21:21:55 +0000159
160/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500161 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
164#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000165
166/*
167 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000169 *
170 * For BR2, need:
171 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
172 * port-size = 32-bits = BR2[19:20] = 11
173 * no parity checking = BR2[21:22] = 00
174 * SDRAM for MSEL = BR2[24:26] = 011
175 * Valid = BR[31] = 1
176 *
177 * 0 4 8 12 16 20 24 28
178 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
179 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000181 * FIXME: the top 17 bits of BR2.
182 */
183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000185
186/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000188 *
189 * For OR2, need:
190 * 64MB mask for AM, OR2[0:7] = 1111 1100
191 * XAM, OR2[17:18] = 11
192 * 9 columns OR2[19-21] = 010
193 * 13 rows OR2[23-25] = 100
194 * EAD set for extra time OR[31] = 1
195 *
196 * 0 4 8 12 16 20 24 28
197 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
198 */
199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
203#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
204#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
205#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000206
207/*
208 * LSDMR masks
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
211#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
212#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
213#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
214#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
215#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
216#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
217#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
218#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
219#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
wdenk03f5c552004-10-10 21:21:55 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
222#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
223#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
224#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
225#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
226#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
227#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
228#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
wdenk03f5c552004-10-10 21:21:55 +0000229
230/*
231 * Common settings for all Local Bus SDRAM commands.
232 * At run time, either BSMA1516 (for CPU 1.1)
233 * or BSMA1617 (for CPU 1.0) (old)
234 * is OR'ed in too.
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \
237 | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \
238 | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
239 | CONFIG_SYS_LBC_LSDMR_BL8 \
240 | CONFIG_SYS_LBC_LSDMR_WRC4 \
241 | CONFIG_SYS_LBC_LSDMR_CL3 \
242 | CONFIG_SYS_LBC_LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000243 )
244
245/*
246 * The CADMUS registers are connected to CS3 on CDS.
247 * The new memory map places CADMUS at 0xf8000000.
248 *
249 * For BR3, need:
250 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
251 * port-size = 8-bits = BR[19:20] = 01
252 * no parity checking = BR[21:22] = 00
253 * GPMC for MSEL = BR[24:26] = 000
254 * Valid = BR[31] = 1
255 *
256 * 0 4 8 12 16 20 24 28
257 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
258 *
259 * For OR3, need:
260 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
261 * disable buffer ctrl OR[19] = 0
262 * CSNT OR[20] = 1
263 * ACS OR[21:22] = 11
264 * XACS OR[23] = 1
265 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
266 * SETA OR[28] = 0
267 * TRLX OR[29] = 1
268 * EHTR OR[30] = 1
269 * EAD extra time OR[31] = 1
270 *
271 * 0 4 8 12 16 20 24 28
272 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
273 */
274
Jon Loeliger25eedb22008-03-19 15:02:07 -0500275#define CONFIG_FSL_CADMUS
276
wdenk03f5c552004-10-10 21:21:55 +0000277#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_BR3_PRELIM 0xf8000801
279#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_INIT_RAM_LOCK 1
282#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
283#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
286#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
287#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
290#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000291
292/* Serial Port */
293#define CONFIG_CONS_INDEX 2
294#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_NS16550
296#define CONFIG_SYS_NS16550_SERIAL
297#define CONFIG_SYS_NS16550_REG_SIZE 1
298#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000301 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
304#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000305
306/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_HUSH_PARSER
308#ifdef CONFIG_SYS_HUSH_PARSER
309#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk03f5c552004-10-10 21:21:55 +0000310#endif
311
Matthew McClintock0e163872006-06-28 10:43:36 -0500312/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600313#define CONFIG_OF_LIBFDT 1
314#define CONFIG_OF_BOARD_SETUP 1
315#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_64BIT_VSPRINTF 1
318#define CONFIG_SYS_64BIT_STRTOUL 1
Jon Loeliger2b40edb2008-03-18 11:12:42 -0500319
Jon Loeliger20476722006-10-20 15:50:15 -0500320/*
321 * I2C
322 */
323#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
324#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk03f5c552004-10-10 21:21:55 +0000325#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
327#define CONFIG_SYS_I2C_SLAVE 0x7F
328#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
329#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk03f5c552004-10-10 21:21:55 +0000330
Timur Tabie8d18542008-07-18 16:52:23 +0200331/* EEPROM */
332#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_I2C_EEPROM_CCID
334#define CONFIG_SYS_ID_EEPROM
335#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
336#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200337
wdenk03f5c552004-10-10 21:21:55 +0000338/*
339 * General PCI
340 * Addresses are mapped 1-1.
341 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600342#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600343#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600344#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600346#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600347#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
349#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000350
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600351#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600352#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600353#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600355#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600356#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
358#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000359
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700360#ifdef CONFIG_LEGACY
361#define BRIDGE_ID 17
362#define VIA_ID 2
363#else
364#define BRIDGE_ID 28
365#define VIA_ID 4
366#endif
wdenk03f5c552004-10-10 21:21:55 +0000367
368#if defined(CONFIG_PCI)
369
370#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200371#define CONFIG_PCI_PNP /* do pci plug-and-play */
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500372#define CONFIG_MPC85XX_PCI2
wdenk03f5c552004-10-10 21:21:55 +0000373
374#undef CONFIG_EEPRO100
375#undef CONFIG_TULIP
376
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500377#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000379
380#endif /* CONFIG_PCI */
381
382
383#if defined(CONFIG_TSEC_ENET)
384
385#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200386#define CONFIG_NET_MULTI 1
wdenk03f5c552004-10-10 21:21:55 +0000387#endif
388
389#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500390#define CONFIG_TSEC1 1
391#define CONFIG_TSEC1_NAME "TSEC0"
392#define CONFIG_TSEC2 1
393#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000394#define TSEC1_PHY_ADDR 0
395#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000396#define TSEC1_PHYIDX 0
397#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500398#define TSEC1_FLAGS TSEC_GIGABIT
399#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500400
401/* Options are: TSEC[0-1] */
402#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000403
404#endif /* CONFIG_TSEC_ENET */
405
wdenk03f5c552004-10-10 21:21:55 +0000406/*
407 * Environment
408 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200409#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200411#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
412#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000413
414#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000416
Jon Loeliger2835e512007-06-13 13:22:08 -0500417/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500418 * BOOTP options
419 */
420#define CONFIG_BOOTP_BOOTFILESIZE
421#define CONFIG_BOOTP_BOOTPATH
422#define CONFIG_BOOTP_GATEWAY
423#define CONFIG_BOOTP_HOSTNAME
424
425
426/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500427 * Command line configuration.
428 */
429#include <config_cmd_default.h>
430
431#define CONFIG_CMD_PING
432#define CONFIG_CMD_I2C
433#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600434#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500435#define CONFIG_CMD_IRQ
436#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500437
wdenk03f5c552004-10-10 21:21:55 +0000438#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500439 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000440#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500441
wdenk03f5c552004-10-10 21:21:55 +0000442
443#undef CONFIG_WATCHDOG /* watchdog disabled */
444
445/*
446 * Miscellaneous configurable options
447 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600449#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
451#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500452#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000454#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000456#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
458#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
459#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
460#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk03f5c552004-10-10 21:21:55 +0000461
462/*
463 * For booting Linux, the board info and command line data
464 * have to be in the first 8 MB of memory, since this is
465 * the maximum mapped by the Linux kernel during initialization.
466 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
wdenk03f5c552004-10-10 21:21:55 +0000468
wdenk03f5c552004-10-10 21:21:55 +0000469/*
470 * Internal Definitions
471 *
472 * Boot Flags
473 */
474#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
475#define BOOTFLAG_WARM 0x02 /* Software reboot */
476
Jon Loeliger2835e512007-06-13 13:22:08 -0500477#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000478#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
479#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
480#endif
481
wdenk03f5c552004-10-10 21:21:55 +0000482/*
483 * Environment Configuration
484 */
485
486/* The mac addresses for all ethernet interface */
487#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500488#define CONFIG_HAS_ETH0
wdenk03f5c552004-10-10 21:21:55 +0000489#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000490#define CONFIG_HAS_ETH1
wdenk03f5c552004-10-10 21:21:55 +0000491#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000492#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000493#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
494#endif
495
496#define CONFIG_IPADDR 192.168.1.253
497
498#define CONFIG_HOSTNAME unknown
499#define CONFIG_ROOTPATH /nfsroot
500#define CONFIG_BOOTFILE your.uImage
501
502#define CONFIG_SERVERIP 192.168.1.1
503#define CONFIG_GATEWAYIP 192.168.1.1
504#define CONFIG_NETMASK 255.255.255.0
505
506#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
507
508#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
509#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
510
511#define CONFIG_BAUDRATE 115200
512
513#define CONFIG_EXTRA_ENV_SETTINGS \
514 "netdev=eth0\0" \
515 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500516 "ramdiskaddr=600000\0" \
517 "ramdiskfile=your.ramdisk.u-boot\0" \
518 "fdtaddr=400000\0" \
519 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000520
521#define CONFIG_NFSBOOTCOMMAND \
522 "setenv bootargs root=/dev/nfs rw " \
523 "nfsroot=$serverip:$rootpath " \
524 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
525 "console=$consoledev,$baudrate $othbootargs;" \
526 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500527 "tftp $fdtaddr $fdtfile;" \
528 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000529
530#define CONFIG_RAMBOOTCOMMAND \
531 "setenv bootargs root=/dev/ram rw " \
532 "console=$consoledev,$baudrate $othbootargs;" \
533 "tftp $ramdiskaddr $ramdiskfile;" \
534 "tftp $loadaddr $bootfile;" \
535 "bootm $loadaddr $ramdiskaddr"
536
537#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
538
wdenk03f5c552004-10-10 21:21:55 +0000539#endif /* __CONFIG_H */